MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 386

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DDR Memory Controller
9.5.9
Transfers to and from memory are always performed in four- or eight-beat bursts (four beats = 32 bytes
when a 64-bit bus is used). For transfer sizes other than four or eight beats, the data transfers are still
operated as four- or eight-beat bursts. If ECC is enabled and either the access is not doubleword aligned
or the size is not a multiple of a doubleword, a full read-modify-write is performed for a write to SDRAM.
If ECC is disabled or both the access is doubleword aligned with a size that is a multiple of a doubleword,
the data masks (MDM[0:8] (MDM[0:4] for 32-bit bus) can be used to prevent the writing of unwanted data
to SDRAM. The DDR memory controller also uses data masks to prevent all unintended full double words
from writing to SDRAM. For example, if a write transaction is desired with a size of one double word
(8 bytes), then the second, third, and fourth beats of data are not written to DRAM.
Table 9-49
the possible transfer sizes with each of the possible starting double-word offsets. All underlined
double-word offsets are valid for the transaction.
9.5.10
The DDR memory controller supports an open/closed page mode with an allowable open page for each
logical bank of DRAM used. In closed page mode for DDR SDRAMs, the DDR memory controller uses
the SDRAM auto-precharge feature, which allows the controller to indicate that the page must be
automatically closed by the DDR SDRAM after the READ or WRITE access. This is performed by using
MA[10] of the address during the COMMAND phase of the access to enable auto-precharge.
Auto-precharge is non-persistent in that it is either enabled or disabled for each individual READ or
WRITE command. It can, however, be enabled or disabled separately for each chip select.
When the DDR memory controller operates in open page mode, it retains the currently active SDRAM
page by not issuing a precharge command. The page remains opens until one of the following conditions
occurs:
9-64
•
•
•
Refresh interval is met.
The user-programmable DDR_SDRAM_INTERVAL[BSTOPRE] value is exceeded.
There is a logical bank row collision with another transaction that must be issued.
lists the data beat sequencing to and from the DDR SDRAM and the data queues for each of
DDR Data Beat Ordering
Page Mode and Logical Bank Retention
1
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
All underlined Double-word offsets are valid for the transaction.
2 double words
3 double words
1 double word
Transfer Size
Table 9-49. Memory Controller–Data Beat Ordering
Starting Double-Word Offset
0
1
2
3
0
1
2
0
1
Double-Word Sequence
DRAM and Queues
0 - 1 - 2 - 3
1 - 2 - 3 - 0
2 - 3 - 0 - 1
3 - 0 - 1 - 2
0 - 1 - 2 - 3
1 - 2 - 3 - 0
2 - 3 - 0 - 1
0 - 1 - 2 - 3
1 - 2 - 3 - 0
1
to/from
Freescale Semiconductor