MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 417

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

10.3.1.5
The vendor identification register (VIR) shown in
the vendor and the device revision.
Table 10-11
10.3.1.6
The processor initialization register in the PIC provides a mechanism for software to reset the processor.
The core_reset signal to the processor is held active until a zero is written to the processor initialization
register field. Thus, PIR should only be written by an external host and the external host should wait at
least 100 µs to clear this field after writing it. The processor should not attempt to write to PIR because
writing to it resets the core; because the core cannot clear the reset field, it would remain in reset
indefinitely.
Note that although the architecture was designed to support multiple processing cores, only fields
corresponding to processors on the device are implemented, as shown in
implementations, only PIR[P0] is implemented.
Freescale Semiconductor
16–23 DEVICE ID Device identification. Vendor-specified identifier for this device. Has no meaning if VENDOR ID = 0.
24–31 VENDOR ID Vendor identification. Specifies the manufacturer of this part. A value of zero implies a generic
8–15
Bits
0–7
Offset 0x4_1090
Offset 0x4_1080
Reset
Reset
W
W
R
R
0
0
Name
STEP
—
describes the VIR fields.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Vendor Identification Register (VIR)
Processor Initialization Register (PIR)
Reserved
Stepping. Indicates the silicon revision for this device. Has no meaning when the VENDOR ID value is zero.
PIC-compliant device.
—
Figure 10-8. Processor Initialization Register (PIR)
Figure 10-7. Vendor Identification Register (VIR)
7
8
Table 10-11. VIR Field Descriptions
STEP
Figure 10-7
All zeros
All zeros
—
15 16
Description
has specific read-only information about
DEVICE ID
Figure
Programmable Interrupt Controller
23 24
10-8. On single-core
VENDOR ID
Access: Read/Write
Access: Read only
30 31
10-21
P0
31