MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 622

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
14.1.3.2
In debug mode, the LBC provides the ID of a transaction source on external device signals. This mode is
enabled on power-on reset, as described in
this mode, the 5-bit internal ID of the current transaction source appears on MSRCID[0:4] whenever valid
address or data is available on the LBC external signals. The reserved value of 0x1F, which indicates
invalid address or data, appears on the source ID signals at all other times. The combination of a valid
source ID (any value except 0x1F) and the value of external address latch enable (LALE) and data valid
(MDVAL) facilitate capturing useful debug data as follows:
14.1.4
The LBC can enter a power-down mode when the system stops the internal (system) clock to the block by
using a handshake protocol initiated by the DEVDISR[LBC] setting in the global utilities block. On
entering power-down mode, the LBC places any SDRAM devices, if used, in self-refresh mode before the
bus clock is stopped. The LBC also allows the PLL sufficient time to recover following the reapplication
of the system clock.
Once the LBC has been put into power-down mode, the only way to exit from this mode is through
HRESET.
14.2
Table 14-1
impedance of designated local bus signals is determined by PORIMPSCR, as described in
Section 19.4.1.3, “POR I/O Impedance Status and Control Register (PORIMPSCR).”
14-4
•
•
If a valid source ID is detected on MSRCID[0:4] and LALE is asserted, a valid full 32-bit address
may be latched from LAD[0:31]. Note that in SDRAM mode the address vector contains the full
address as {row, bank, column, lsbs} where row corresponds to the same row address for the given
column address and lsbs are the unconnected lsbs of the address for a given port size.
If a valid source ID is detected on MSRCID[0:4] and MDVAL is asserted, valid data may be
latched from LAD[0:31].
LSDDQM n /
LSDA10/
LSDWE/
External Signal Descriptions
contains a list of external signals related to the LBC and summarizes their function. I/O
LGPL0
LGPL1
LWE n /
Name
LALE
LBS n
LCS
Power-Down Mode
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Source ID Debug Mode
Number of
Signals
1
8
4
1
1
Table 14-1. Signal Properties—Summary
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Section 21.4.3, “Local Bus Interface Debug.”
External address latch enable
Chip selects
GPCM mode: write enable
SDRAM mode: byte lane data mask
UPM mode: byte (lane) select
SDRAM mode: row address bit/command bit
UPM mode: general-purpose line 0
SDRAM mode: write enable
UPM mode: general-purpose line 1
Function
Freescale Semiconductor
When placed in