MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 961

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

16.4
This section describes the function of the DMA controller.
16.4.1
All DMA channels support two different modes of operation: a basic mode (MRn[XFE] is cleared) and an
extended mode (MRn[XFE] is set). In both modes, a channel can be activated by clearing and setting
MRn[CS], or through the single-write start mode using MRn[CDSM/SWSM] and MRn[SRW], or through
an external control mode using MRn[ECS_EN].
In basic mode, the channel can be programmed in basic direct mode or basic chaining mode. In extended
mode, the channel can be programmed in extended direct mode or extended chaining mode. Extended
mode provides more capabilities, such as extended descriptor chaining, striding capabilities, and a more
flexible descriptor structure.
The DMA controller supports misaligned transfers for both the source and destination addresses. In order
to maximize performance, the source and destination engines align the source and destination addresses to
a 64-byte boundary. The DMA always reads/writes the maximum number of bytes for a given transfer as
Freescale Semiconductor
Bits
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
EOLNI2
EOLSI2
EOLNI3
EOLSI3
Functional Description
EOSI2
EOSI3
Name
CH2
CB2
CH3
CB3
TE2
PE2
TE3
PE3
—
—
DMA Channel Operation
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Transfer error, channel 2
0 Normal operation
1 An error condition occurred during the DMA transfer.
Reserved
Channel halted, channel 2
Programming error, channel 2
End-of-links interrupt, channel 2
Channel busy, channel 2
End-of-segment interrupt, channel 2
End-of-lists/direct interrupt, channel 2
Transfer error, channel 3
0 Normal operation
1 An error condition occurred during the DMA transfer.
Reserved
Channel halted, channel 3
Programming error, channel 3
End-of-links interrupt, channel 3
Channel busy, channel 3
End-of-segment interrupt, channel 3
End-of-lists/direct interrupt, channel 3
Table 16-20. DGSR Field Descriptions (continued)
Description
DMA Controller
16-25