MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 808

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
15.5.3.5.15 MAC Exact Match Address 1–15 Part 1 Registers
The MAC01ADDR1–MAC15ADDR1 registers are written by the user with the unicast or multicast
addresses aliasing the MAC.
registers. The value of the address written into MACxADDR1 and MACnADDR2 is byte reversed from
how it would appear in the DA field of a frame in memory. For example, for a MAC address of
0x12345678ABCD, MACnADDR1 is set to 0xCDAB7856 and MACnADDR2 is set to 0x34120000. For
any valid, non-zero MAC address received, exact match registers can be excluded individually by clearing
them to all zero bytes.
Table 15-51
15.5.3.5.16 MAC Exact Match Address 1–15 Part 2 Registers
The MAC01ADDR2–MAC15ADDR2 registers are written by the user with the unicast or multicast
addresses aliasing the MAC.
registers.
15-78
Offset eTSEC1:0x2_4548+8× n ; eTSEC3:0x2_6548+8× n
Reset
Offset eTSEC1:0x2_454C+8× n ; eTSEC3:0x2_654C+8× n
Reset
W
W
R
R
16–23 Exact Match Address, 4th Octet Holds the fourth octet of the exact match address. The fourth octet
24–31 Exact Match Address, 3rd Octet Holds the third octet of the exact match address. The third octet
8–15 Exact Match Address, 5th Octet Holds the fifth octet of the exact match address. The fifth octet
0–7
Bit
0
0
Exact Match Address,
Exact Match Address,
describes the fields of a MACnADDR1 register.
Exact Match Address, 6th Octet Holds the sixth octet of the exact match address. The sixth octet
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
(MAC01ADDR1–MAC15ADDR1)
(MAC01ADDR2–MAC15ADDR2)
2nd Octet
6th Octet
Figure 15-50. MAC Exact Match Address n Part 1 Register Definition
Figure 15-51. MAC Exact Match Address x Part 2 Register Definition
Name
Figure 15-50
Figure 15-51
Table 15-53. MAC n ADDR1 Field Descriptions
7
7
8
8
Exact Match Address,
Exact Match Address,
(destination address bits 40
(destination address bits 32
(destination address bits 24
(destination address bits 16
5th Octet
1st Octet
describes the definition for all of the fifteen MACnADDR1
describes the definition for all of the fifteen MACxADDR2
All zeros
All zeros
15 16
15 16
Exact Match Address,
–
–
–
–
Description
47) defaults to a value of 0x0.
39) defaults to a value of 0x0.
31) defaults to a value of 0x0.
23) defaults to a value of 0x0.
4th Octet
23 24
—
Exact Match Address,
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
3rd Octet
31
31