MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 976

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DMA Controller
16.5.1
The following is a description of unusual DMA paths including explanations of why some functional
blocks cannot serve as DMA targets. The following topics are addressed:
16.5.1.1
The L1 cache cannot be a direct DMA target because it cannot be directly addressed by software. However,
DMA access into the L1 cache occurs indirectly if a block of memory that is cached in the L1 is specified
as the DMA target. This effect is deterministic if the target memory block was locked into the L1 with
cache locking instructions.
16.5.1.2
The Ethernet controllers cannot serve as DMA targets because they have no suitable internal memory for
this purpose. The Ethernet controllers have dedicated DMA channels to move data between the external
transmit and receive buffers and the internal packet buffer. This dedicated channel is the only DMA service
to the internal packet buffers.
However, Ethernet ports can serve as DMA targets by using a general-purpose DMA controller to access
the transmit and receive buffers defined by the Ethernet buffer descriptors. Because Ethernet data buffers
are located in RAM outside of the Ethernet controllers, general-purpose DMA engines can move data to
or from these memory regions. Also, because Ethernet controllers automatically read buffer descriptors
and send (or load) data buffers, a DMA transfer into (or out of) these buffers is effectively a transfer into
(or out of) the Ethernet ports.
16.5.1.3
Because any internal register can be addressed with the four-channel DMA controller, configuration,
control, and status registers throughout the device are valid DMA targets. However, the primary purpose
of DMA—to reduce processor load by moving large blocks of data— is not served by DMA transfers of
configuration data. For example, while it is possible to DMA into the I
interrupt controller (PIC), doing so is extremely inefficient and is seldom beneficial in normal operation.
The overhead of creating DMA descriptors far exceeds any savings in CPU cycles.
16.5.1.4
The I
“DMA to Configuration, Control, and Status Registers,”
data register (I2CDR).
16-40
•
•
•
•
2
C controller is not transparent to DMA transfers. Observe the caveats listed in
Transaction initiators (masters)
DMA targets, that is, data sources or destinations
Transparency of the bus controllers to DMA transactions
What is useful as opposed to what is possible. For example, any register can be addressed through
an internal control bus, which means configuration and control registers can be DMA targets.
Unusual DMA Scenarios
DMA to e500 Core
DMA to Ethernet
DMA to Configuration, Control, and Status Registers
DMA to I
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
C
when accessing any I
2
C controller or programmable
2
C register, including the
Freescale Semiconductor
Section 16.5.1.3,