MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 528

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
12.4.3.10.2 AFEU Context Memory Pointer Register
The context memory pointer register holds the internal context pointers that are updated with each byte of
message processed. These pointers correspond to the values of I, J, and Sbox[I+1] in the ARC-4 algorithm.
If this register is written during message processing, a context error will be generated.
When performing ARC-4 operations, the user has the option of performing a new S-box permutation per
packet, or unloading the contents of the S-box (context) and reloading this context prior to processing of
the next packet. The S-box contents (256 bytes) plus the three bytes of the context memory pointers are
unloaded and reloaded via the AFEU FIFOs.
AFEU context consists of the contents of the S-box, as well as three counter values, which indicate the
next values to be used from the S-box. Context must be loaded in the same order in which it was unloaded.
12.4.3.11 AFEU Key Registers 0–1 (AFEUK n )
AFEU uses two write-only key registers to guide initial permutation of the AFEU S-box, in conjunction
with the AFEU key size register. AFEU performs permutation starting with the first byte of key register 1,
and uses as many bytes from the two key registers as necessary to complete the permutation. Reading
either of these memory locations generates an address error interrupt.
12.4.3.12 AFEU FIFOs
The AFEU uses an input FIFO/output FIFO pair to hold data before and after the encryption process. These
FIFOs are multiply addressable, but those multiple addresses point only to the appropriate end of the
appropriate FIFO. A write to anywhere in the AFEU FIFO address space causes the 64-bit-word to be
pushed onto the AFEU input FIFO, and a read from anywhere in the AFEU FIFO address space causes a
64-bit-word to be popped off of the AFEU output FIFO. Overflows and underflows caused by reading or
writing the AFEU FIFOs are reflected in the AFEU interrupt status register.
12.4.4
Message Digest Execution Unit (MDEU)
This section contains details about the message digest execution unit (MDEU), including modes of
operation, status and control registers, and FIFOs.
Most of the registers described here would not normally be accessed by the host. They are documented
here mainly for debug purposes. In typical operation, the MDEU is used through channel-controlled
access, which means that most reads and writes of MDEU registers are directed by the SEC channels.
Driver software performs host-controlled register accesses on only a few registers for initial configuration
and error handling.
12.4.4.1
MDEU Mode Register (MDEUMR)
The MDEU mode register is used to program the function of the MDEU. Bits 56–63 of this register are
specified by the user through the MODE0 or MODE1 field of the descriptor header. The remaining bits
are supplied by the channel and thus are not under direct user control.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
12-50
Freescale Semiconductor