MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 305

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
dcbtls_L2
dcbtstls_L2
Write-through store
Cache-inhibited store
Cache-inhibited stwcx
dcblc_L2
icblc_L2
Victim castout
dcbt_L2
icbt_L2
dcbtst_L2
dcbtls_L2
icbtls_L2
dcbtstls_L2
Snoop push
dcbf
dcbst
dcbz
dcba
Source of Transaction
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 7-27. State Transitions Due to Core-Initiated Transactions (continued)
I,E,M
I,E,M
Initial States
dL1
dL1
N/A
N/A
dL1
dL1
dL1
dL1
dL1
dL1
I,E
L1
M
M
M
M
I
E/EL/T
I/E/EL
E/EL
E/EL
E/EL
EL/T
EL/T
EL/T
EL
I/E
I/E
EL
L2
I/T
I/E
I/T
I/E
I/E
EL
T
E
T
T
T
I
I
I
I
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Hit
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
L2
same
same
same
same
same
Final States
N/A
N/A
N/A
N/A
I/E
I/E
L1
M
M
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Same L2CTL[L2IO] = 0.
same Read-modify-write
same
same L2CTL[L2IO] = 1. If software sharing cache lines
EL
EL
EL
EL
EL
EL
L2
I/T
T
T
T
T
E
E
T
T
I
I
I
I
I
I
I
I
I
L2CTL[L2IO] = 1
L2CTL[L2IO] = 1
L2CTL[L2IO] = 1
L2CTL[L2IO] = 1
L2CTL[L2IO] = 0
L2CTL[L2IO] = 0
L2CTL[L2IO] = 0. Restore locked line with valid
data from bus
Invalidate line
Invalidate data, keep lock
Invalidate line
Invalidate data, keep lock
between instructions and data wishes to capture
instruction lines in L2 with L2CTL[L2IO] = 1, it must
perform dcbst to flush the line out of the dL1 before
fetching it into L2.
L2CTL[L2IO] = 0
L2CTL[L2IO] = 1.
L2CTL[L2IO = 0.
An icbtls_L2 that hits modified in L1 cannot be
distinguished from dcbtls_L2 and sets the L2 dlock
bit. If software shares cache lines between
instructions and data and wishes to set hillocks in
L2, it must perform dcbst to flush the line out of the
dL1 before locking it in L2.
Invalidate data, keep lock
Comments
L2 Look-Aside Cache/SRAM
7-37