MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 718

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
The connections are specified as follows:
14-100
•
•
•
•
One chip select, LCSn (whatever is available in the system), is used to memory map accesses from
the host local bus to the HDI16 MSC8101 HDI16 peripheral, and is connected to the HDI16 chip
select line (HCS).
This interface uses two separate general-purpose strobe lines (LGPL1 and LGPLy):
— LGPL1 is programmed to generate the HDI16 read/write signal (HRDRW), which is typically
— LGPLy is programmed to generate the HDI16 data strobe (HDS), which must be asserted every
Data lines—The bus data lines (LADn) are directly connected to the HDI16 data lines (HDn).
DMA request/service request signals (HRRQ and HTRQ)—as appropriate in the application
high for a read access and low for write access. In any case, the host port requires a HR/W
signal. This can be generated by using LGPL1, and allows it to adopt the timing virtually
without restrictions. Alternatively the designer can invert LBCTL to generate this signal. It is
the responsibility of the UPM pattern designer to plan for the additional delay of that inverter
in the UPM pattern to satisfy the AC timings at the DSP host port.
16-bit read or write transaction.
HRRQ/HACK
HTRQ/HREQ
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MSC8101
Signal(s)
HDS
Local Bus Interface
Table 14-44. Local Bus to MSC8101 HDI16 Connections (continued)
or inverted LBCTL
in application
As required
LAD[0:31]
LA[27:28]
LA[29:30]
LGPL1
Type
LGPLy
LCS n
LALE
O
O
I
Figure 14-81. Interface to MSC8101 HDI16
Host data strobe signal
Receive host request OP
Transmit host request OP
Description
LAD[0:15]
Latch
LGPLy
As required in application
As required in application
Connect with Local Bus Signal
HCS2
HD[0:15]
HA[0:1]
HA[2:3]
HCS1
HRDRW
HDS
HRRQ/HACK
HTRQ/HREQ
MSC8101
Freescale Semiconductor