MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1054

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI Express Interface Controller
side) plus the block base address, plus the offset of the specific register to be accessed. Note that all
memory-mapped registers (except the PCI Express configuration data register, PEX_CONFIG_DATA)
must only be accessed as 32-bit quantities.
Also note that although the table explicitly lists only the registers for the PCI Express Controller 1, the
register map for PCI Express Controllers 2 and 3 are the same except for the block base address.
Memory-mapped registers for PCI Express Controller 1 begin at block base address 0x0_A000, controller
2 registers begin at 0x0_9000, and controller 3 registers begin at 0x0_B000.
Table 18-3
descriptions, the following access definitions apply:
18-6
0x018–
0x030–
Offset
0x00C
0x01C
0x02C
0xBF4
0x000
0x004
0x008
0x010
0x014
0x020
0x024
0x028
•
•
•
•
•
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
PEX_CONFIG_ADDR—PCI Express configuration address register
PEX_CONFIG_DATA—PCI Express configuration data register
Reserved
PEX_OTB_CPL_TOR—PCI Express outbound completion timeout
register
PEX_CONF_RTY_TOR—PCI Express configuration retry timeout
register
PEX_CONFIG—PCI Express configuration register
Reserved
PEX_PME_MES_DR—PCI Express PME & message detect register
PEX_PME_MES_DISR—PCI Express PME & message disable
register
PEX_PME_MES_IER—PCI Express PME & message interrupt enable
register
PEX_PMCR—PCI Express power management command register
Reserved
lists the memory-mapped registers. In this table and in the register figures and field
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Express Controller 1Memory-Mapped Registers—Block Base Address 0x0_A000
Table 18-3. PCI Express Memory-Mapped Register Map
PCI Express Power Management Event & Message Registers
PCI Express Configuration Access Registers
PCI Express IP Block Revision Registers
Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
—
—
0x0010_FFFF
0x0400_FFFF
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
—
—
Freescale Semiconductor
18.3.2.2/18-10
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