MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 115

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

1.3.10
The MPC8533E provides a boot sequencer that uses the I
and loads the data into the MPC8533E configuration registers. The boot sequencer is enabled by a
configuration pin sampled at the negation of the MPC8533E hardware reset signal. If enabled, the boot
sequencer holds the MPC8533E processor core in reset until the boot sequence is complete. If the boot
sequencer is not enabled, the processor core exits reset and fetches boot code in default configurations.
1.3.11
The MPC8533E includes a DUART intended for use in maintenance, bringing-up, and debugging of
systems. The MPC8533E provides a standard four-wire handshake (SIN, SOUT, RTS, CTS) for each port.
The DUART is a slave interface. An interrupt is provided to the interrupt controller or optionally steered
externally to allow device handshakes. Interrupts are generated for transmit, receive, line status, and
MODEM status.
The MPC8533E DUART supports full-duplex operation. It is compatible with the PC16450 and PC16550
programming models. Also, 16-byte FIFOs are supported for both the transmitter and the receiver.
Software programmable baud generators divide the system clock to generate a 16x clock. Serial interface
data formats (data length, parity, 1/1.5/2 stop bits, baud rate) are also software selectable.
1.3.12
The MPC8533E local bus controller (LBC) port allows connections with a wide variety of external
memories, DSPs, and ASICs. Three separate state machines share the same external pins and can be
programmed separately to access different types of devices. The general-purpose chip select machine
(GPCM) controls accesses to asynchronous devices using a simple handshake protocol. The user
programmable machine (UPM) can be programmed to interface to synchronous devices or custom ASIC
interfaces. The SDRAM controller provides access to standard SDRAM. Each chip select can be
configured so that the associated chip interface can be controlled by the GPCM, UPM, or SDRAM
controller. All may exist in the same system.
The GPCM provides a flexible asynchronous interface to SRAM, EPROM, FEPROM, ROM, and other
devices such as asynchronous DSP host interfaces and CAMs. Minimal glue logic is required. Handshake
signals can be configured to transition on fractions of the system clock. The GPCM does not support
bursting.
The UPM allows an extremely flexible interface in which the programmer configures each of a set of
general-purpose protocol signals by writing the transition pattern into a memory array. The UPM supports
synchronous and bursting interfaces. It also supports multiplexed addressing so that a simple DRAM
interface can be implemented. The UPM is entirely flexible in order to provide a very high degree of
customization with respect to both asynchronous and burst-synchronous interfaces, which permits glueless
or almost glueless connection to burst SRAM, custom ASIC, and synchronous DSP interfaces.
The LBC provides a synchronous DRAM (SDRAM) machine that provides the control functions and
signals for glueless connection to JEDEC–compliant SDRAM devices. An internal PLL (phase-locked
loop) for bus clock generation ensures improved data setup margins for board designs. The SDRAM
Freescale Semiconductor
Boot Sequencer
Dual Universal Asynchronous Receiver/Transmitter (DUART)
Local Bus Controller
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
C interface to access an external serial ROM
Overview
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