MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1154

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI Express Interface Controller
18.4.2
Both INTx and message signaled interrupts (MSI) are supported; however there are subtle differences
depending on whether the PCI Express controller is configured as an RC or EP device.
18.4.2.1
18.4.2.1.1
Hardware INTx message generation is not supported in EP mode.
18.4.2.1.2
In EP mode, the PCI Express controller can be configured to automatically generate MSI transactions to
the root complex when an interrupt event occurs. The PCI Express controller uses irq_out (an internal
version of the IRQ_OUT signal) to trigger the generation of the MSI. To trigger the MSI, interrupt events
must be routed to the to irq_out by setting the EP (external pin) bit in the associated Interrupt Destination
register in the PIC. Note that the IRQ_OUT signal should not be used for any other function if it is being
used to trigger MSI transactions.
The remote root complex is expected set up the MSI capability structure of all endpoints at system
initialization by filling the Message Address and Message Data registers with appropriate values and
setting the MSIE bit in the MSI Message Control register.
With the PCI Express controller properly configured, when it detects the leading edge of irq_out going
active, it generates a PCI Express memory write transaction to the address specified in the MSI Message
Address register (and MSI Message Upper Address register) with a data payload as specified in the MSI
Message Data register (with leading zeros appended).
18-106
Vendor_Defined Type 1
Attention_Indicator_On
Attention_Indicator_Blink
Attention_Indicator_Off
Power_Indicator_On
Power_Indicator_Blink
Power_Indicator_Off
Attention_Button_Pressed
Interrupts
EP Interrupt Generation
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Hardware INTx Message Generation
Hardware MSI Generation
Name
Table 18-121. PCI Express EP Inbound Message Handling (continued)
0100 0011
0100 0101
0100 0111
0100 0100
Code[7:0]
0111 1111
0100 0001
0100 0000
0100 1000
Routing[2:0]
100
100
100
100
100
100
100
No action taken
Set PEX_PME_MES_DR[AION] bit. Send interrupt
if enabled.
Set PEX_PME_MES_DR[AIB] bit. Send interrupt if
enabled.
Set PEX_PME_MES_DR[AIOF] bit. Send interrupt if
enabled.
Set PEX_PME_MES_DR[PION] bit. Send interrupt
if enabled.
Set PEX_PME_MES_DR[PIB] bit. Send interrupt if
enabled.
Set PEX_PME_MES_DR[PIOF] bit. Send interrupt if
enabled.
No action taken
Action
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