MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 574

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
12-96
Bits
38
39
40
41
42
43
44
45
46
Name
PRD
SRD
Table 12-52. Crypto-Channel Pointer Status Register Field Descriptions (continued)
MO
PR
SR
PG
SG
PD
MI
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Multi_EU_IN. The Multi_EU_IN bit indicates whether data input snooping will be performed, as
determined by the snoop type bit in the descriptor header.
0 Data input snooping by secondary EU disabled.
1 Data input snooping by secondary EU enabled.
Multi_EU_OUT. The Multi_EU_OUT bit indicates whether data output snooping will be performed, as
determined by the snoop type bit in the descriptor header.
0 Data output snooping by secondary EU disabled.
1 Data output snooping by secondary EU enabled.
PRI_REQ. Request primary EU assignment.
0 Primary EU assignment request is inactive.
1 The channel is requesting assignment of primary EU to the channel. The channel will assert the EU
The PRI_REQ bit is set when descriptor processing is initiated by the channel and the Op_0 field in the
descriptor header contains a valid EU identifier. This bit is cleared when the request is granted, which
will be reflected in the status register by the setting the PRI_GRANT bit.
SEC_REQ. Request secondary EU assignment.
0 Secondary EU assignment request is inactive.
1 The channel is requesting assignment of secondary EU to the channel. The channel will assert the
The SEC_REQ bit is set when descriptor processing is initiated by the channel and the Op_1 field in
the descriptor header contains a valid EU identifier. This bit is cleared when the request is granted,
which will be reflected in the status register by the setting the SEC_GRANT bit.
Primary EU granted. The PRI_GRANT bit reflects the state of the EU grant signal for the requested
primary EU from the controller.
0 The primary EU grant signal is inactive.
1 The EU grant signal is active indicating the controller has assigned the requested primary EU to the
secondary EU from the controller.
0 The secondary EU grant signal is inactive.
1 The EU grant signal is active indicating the controller has assigned the requested secondary EU to
assigned primary EU.
0 The assigned primary EU reset done signal is inactive.
1 The assigned primary EU reset done signal is active indicating its reset sequence has completed
the assigned secondary EU.
0 The assigned secondary EU reset done signal is inactive.
1 The assigned secondary EU reset done signal is active indicating its reset sequence has completed
EU.
0 The assigned primary EU done interrupt is inactive.
1 The assigned primary EU done interrupt is active indicating the EU has completed processing and
Secondary EU granted. The SEC_GRANT bit reflects the state of the EU grant signal for the requested
Primary EU reset done. The PRI_RST_DONE bit reflects the state of the reset done signal from the
Secondary EU reset done. The SEC_RST_DONE bit reflects the state of the reset done signal from
Primary EU done. The PRI_DONE bit reflects the state of the done interrupt from the assigned primary
request signal indicated by the op0 field in the descriptor header register as long as this bit remains
set.
EU request signal indicated by the Op_1 field in the descriptor header register as long as this bit
remains set.
channel.
the channel.
and it is ready to accept data.
and it is ready to accept data.
is ready to provide output data.
Description
Freescale Semiconductor