MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 556

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
The context for CCM decryption/MAC generation is:
CCM decryption processing is the reverse of encryption. With the session specific key and context, the
AESU performs the following operations:
12-78
5. The counter value is incremented, and is then encrypted with the symmetric key. The result is then
6. The counter continues to be incremented, and encrypted with the symmetric key, with the result
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1. Initialize the IV, and encrypt with the symmetric key. Simultaneously, the counter (initial counter
2. The 802.11 frame header is hashed with the encrypted IV. (The AESU automatically determines
3. As each ciphertext block is converted to plaintext, the plaintext is CBC encrypted. When the final
to memory (per the descriptor pointer) for the host to append to the 802.11i frame. Note: The MIC
written out to memory by the AESU is the full 128 bits. The host must only append the most
significant 64 bits to the frame as the MIC.
hashed with the first block of plaintext to produce the first block of cipher text. The ciphertext is
placed in the AESU output FIFO.
hashed with each successive block of plaintext, until all plaintext has been converted to ciphertext.
The SEC controller will manage FIFO reads and writes, fetching plaintext and writing ciphertext
per the pointers provided in the descriptor. When all ciphertext and the MIC has been output, the
CCM encrypt operation is complete.
Reg 1
Reg 3
Reg 5
Reg 7 Counter modulus exponent (msb<--lsb) Should be fixed at 0x0000_0080.
value) from context registers 5–6 is encrypted with the symmetric key. The result is hashed with
the encrypted MAC (from context register 3–4), and the resulting original MAC is written to
context register 3–4, overwriting the encrypted MAC.
Note: Strictly speaking, the counter is encrypted with the symmetric key; however, the AESU
should be set for decrypt to perform the counter and CBC processes in the correct order.
the header length.) Simultaneously, the counter is incremented, and is then encrypted with the
symmetric key. The result is then hashed with the first block of ciphertext to produce the first block
of plaintext. The plaintext is placed in the AESU output FIFO, while simultaneously, in CBC
fashion, a copy of the first block of plaintext is hashed with the output of encryption of the 802.11
frame header. The output is encrypted with the symmetric key.
plaintext block has been processed, the CBC MAC (MAC tag) is written to context registers 1-2.
The first 64 bits of the MAC tag are compared to the MAC tag recovered in step 1.
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MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2 Session-specific128-bit initialization vector (from memory)
4 MIC (from received frame) + 64 bits of zero padding
6 Session-specific counter (initial counter value) (from memory)
The counter modulus for CCM mode is currently defined as 2
the exponent 128. This value has been made programmable in the SEC to in
case the final version of 802.11i uses a different counter modulus. Because
this is a programmable field, it must be generated and stored along with
other session specific information for loading into the AESU context
register prior to CCM decryption.
NOTE
128
, making
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