MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 527

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.4.3.9
The EU go register in the AFEU, displayed in
processed has been written to the input FIFO. This allows the AFEU to perform special processing when
it reaches the last block of data. Before this register is written, the AFEU will not process the last block of
data in its input FIFO. After this register is written, the AFEU continues to perform normal processing on
all but the last block of data, then it goes on to processes the last block, using the value in the data size
register to determine how much of the block to process. The data size register specifies the number of bits
to process, which is a multiple of 8, from 8 to 64. After processing of the last block is completed, the AFEU
signals DONE. If the dump context bit in the AFEU mode register is set, the context is written to the output
FIFO following the last message word. A read of the AFEUEUG register always returns a zero value.
12.4.3.10 AFEU Context
This section provides additional information about the AFEU context memory and its related pointer
register.
12.4.3.10.1 AFEU Context Memory
The S-box memory consists of 32 64-bit words, each readable and writable. The S-box contents should not
be written with data unless it was previously read from the S-box. Context data may only be written if the
prevent permutation mode bit is set (see
message data. If the context registers are written during message processing or the prevent permutation bit
is not set, a context error will be generated. Reading this memory while the module is not done generates
an error interrupt.
Freescale Semiconductor
Address 0x3_1BF8
Bits
Reset
59
60
61
62
63
W
R
0
Name
OFU
IFO
IFE
—
—
AFEU EU Go Register (AFEUEUG)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 12-25. AFEU Interrupt Control Register Field Descriptions (continued)
Input FIFO error. The AFEU input FIFO was detected non-empty upon generation of done interrupt.
0 Input FIFO non-empty error enabled
1 Input FIFO non-empty error disabled
Reserved
Input FIFO overflow. The AFEU input FIFO was pushed while full.
0 Input FIFO overflow error enabled
1 Input FIFO overflow error disabled
Output FIFO underflow. The AFEU output FIFO was read while empty.
0 Output FIFO underflow error enabled
1 Output FIFO underflow error disabled
Reserved
Figure 12-28. AFEU EU Go Register
Figure
Figure
12-21) and the context data must be written prior to the
AFEU EU_GO
All zeros
12-28, is used to signal the AFEU that all data to be
Description
Security Engine (SEC) 2.1
Access: Write-only
12-49
63