MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 432

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MPC8533EVTAQGA

Manufacturer Part Number
MPC8533EVTAQGA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTAQGA

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.0GHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8533EVTAQGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Programmable Interrupt Controller
Table 10-34
10.3.6
This section contains the description of all of the shared message signaled interrupt registers.
10.3.6.1
The shared message signaled interrupt registers shown in
sources sharing the message register have pending interrupts. Up to 32 sources can share any individual
message register. These registers are cleared when read. A write to these registers has no effect.
Table 10-35
10.3.6.2
This register shown in
status bit is set to 1 when the corresponding shared message signaled interrupt is active. The status bit is 0
if all the corresponding shared interrupt sources are cleared in the shared message signaled interrupt
register (MSIR). This register is read-only.
10-36
28–31
0–27
Offset 0x4_1600, 0x4_1610, 0x4_1620, 0x4_1630, 0x4_1640, 0x4_1650, 0x4_1660, 0x4_1670
Reset
Reset All zeros (Note: After reset, read the MSIRs to ensure that any interrupts previously pending are cleared).
Bits
31–0
Bits Name
W
W
R
R
SH31
SH15
S3–S0 Status n . Reports status of messaging interrupt 3. Writing a 1 clears this field.
SH n
Name
16
0
describes the MSR fields.
describes the bits of the MSIRs.
Shared Message Signaled Registers
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
SH30
SH14
Message sharer n ( n = 31–0) has a pending interrupt.
Shared Message Signaled Interrupt Registers (MSIRs)
Shared Message Signaled Interrupt Status Register (MSISR)
Reserved
0 Messaging interrupt n is not active.
1 Messaging interrupt n is active.
17
1
Figure 10-31. Shared Message Signaled Interrupt Register (MSIRs)
SH29
SH13
18
2
Figure 10-32
SH28
SH12
19
3
SH27
SH11
20
Table 10-35. MSIRs Field Descriptions
4
Table 10-34. MSR Field Descriptions
contains the status bits for the shared message signaled interrupts. The
SH26
SH10
21
5
SH25
SH9
22
6
SH24
SH8
23
7
All zeros
Description
Description
SH23
SH7
Figure 10-31
24
8
SH22
SH6
25
9
SH21
SH5
10
26
indicate which of the interrupt
SH20
SH4
11
27
SH19
SH3
12
28
Freescale Semiconductor
SH18
SH2
13
29
Access: Special
SH17
SH1
14
30
SH16
SH0
15
31

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