MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 517

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.4.2.7
The interrupt control register controls the result of detected errors. For a given error (as defined in
Section 12.4.2.6, “DEU Interrupt Status Register
set, then the error is ignored; no bit is set in the DEU interrupt status register, and no error interrupt
occurs.If the corresponding bit is not set, then upon detection of an error, the interrupt status register is
updated to reflect the error, causing assertion of the error interrupt signal, and causing the module to halt
processing.
Freescale Semiconductor
Address DEU 0x3_2038
0–49
Bits Name
Bits Name
62
63
50
51
52
53
Reset
W
R
OFU Output FIFO underflow. The DEU output FIFO was read while empty.
OFO Output FIFO overflow. The DEU output FIFO was pushed while full.
KPE
ERE
CE
0
—
IE
0 No error detected
1 Output FIFO has underflow error
0 No error detected
1 Output FIFO has overflowed
Reserved
Key parity error. The defined parity bits in the keys written to the key registers did not reflect odd parity correctly.
(Note that key register 2 and key register 3 are only checked for parity if the appropriate DEU mode register bit
indicates triple DES.
0 Key parity error enabled
1 Key parity error disabled
Internal error. An internal processing error was detected while performing encryption.
0 Internal error enabled
1 Internal error disabled
Early read error. The DEU IV register was read while the DEU was performing encryption.
0 Early read error enabled
1 Early read error disabled
Context error. A DEU key register, the key size register, the data size register, the mode register, or IV register
was modified while DEU was performing encryption.
0 Context error enabled
1 Context error disabled
DEU Interrupt Control Register (DEUICR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 12-19. DEU Interrupt Status Register Field Descriptions (continued)
Table 12-20. DEU Interrupt Control Register Field Descriptions
—
Figure 12-19. DEU Interrupt Control Register
49
KPE IE ERE CE KSE DSE ME AE OFE IFE IFU IFO OFU OFO
50
(DEUISR)”), if the corresponding bit in this register is
51
Description
Description
52
3000
53
54
55
56
57
58
59
Security Engine (SEC) 2.1
60
Access: Read/Write
61
62
12-39
63