MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 424

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

22–23 CLKR Clock ratio. Specifies the ratio of the timer frequency to the platform (CCB) clock. The following clock ratios are
24–28
29–31 CASC Cascade timers. Specifies the output of particular global timers as input to others.
Programmable Interrupt Controller
10.3.3
The summary registers indicate the interrupt sources directed to IRQ_OUT or cint. Summary register bits
are cleared when the corresponding interrupt that caused a bit to be set is negated. Note that only
level-sensitive interrupts can be directed to IRQ_OUT or cint.
The IRQ_OUT summary registers, shown in
interrupt source. The corresponding bit is set if the interrupt is active and is directed to IRQ_OUT (that is,
if the corresponding xIDR[EP] is set).
The critical interrupt summary registers shown in
each interrupt source. The corresponding bit is set if the interrupt is active and is directed to the processor’s
critical interrupt signal cint (if the CI field in its corresponding destination register is set). The summary
register bits are cleared when the corresponding interrupt that caused a bit to be set is negated.
Note that unused IRQn signals may be used as general-purpose inputs. The external interrupt summary
register (ERQSR) can be used to monitor these signals. See
Register
10.3.3.1
10-28
Bits Name
—
(ERQSR),” and
supported:
00 Default. Divide by 8
01 Divide by 16
10 Divide by 32
11 Divide by 64
Reserved
000 Default. Timers not cascaded
001 Cascade timers 0 and 1
010 Cascade timers 1 and 2
011 Cascade timers 0, 1, and 2
100 Cascade timers 2 and 3
101 Cascade timers 0 and 1; timers 2 and 3
110 Cascade timers 1, 2, and 3
111 Cascade timers 0, 1, 2, and 3
External, IRQ_OUT, and Critical Interrupt Summary Registers
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
External Interrupt Summary Register (ERQSR)
The fields in ERQSR report only the current state of IRQ0–11. These fields
were designed to work with level-sensitive interrupts; the values returned
for edge-sensitive interrupts may be unreliable.
Section 19.5.2, “General-Purpose I/O
Table 10-21. TCR Field Descriptions (continued)
Figure 10-19
NOTE
Figure 10-22
Description
Section 10.3.3.1, “External Interrupt Summary
through
Signals,” for more information.
through
Figure 10-21
Figure 10-24
contain one bit for each
Freescale Semiconductor
contain one bit for