MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 953

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Offset 0x118
Reset
Table 16-10
16.3.1.6
The destination attributes registers, shown in
operation. Stride mode is enabled by setting DATRn[DSME].
If DATRn[DBPATMU] is cleared, the target interface is derived from the local access ATMU mapping and
the transaction is obtained from the value specified in DATRn[DWRITETTYPE] using the local address
space category.
Freescale Semiconductor
W
R
0–31
Offset 0x114
Reset
Bits
0x198
0x218
0x298
0
W
R
—
1
0x194
0x214
0x294
0
Name
SAD
DPBATMU — DTFLOWLVL DPCIORDER DSME DTRANSINT DWRITETTYPE
describes the field of the SARn.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Destination Attributes Registers (DATR n )
2
Source address. This register contains the low-order bits of the 36-bit source address of the DMA transfer.
The contents are updated after every DMA write operation unless the final stride of a striding operation is less
than the stride size, in which case it remains equal to the address from which the last stride began.
3
Figure 16-11. Destination Attributes Registers (DATR n )
4
Figure 16-10. Source Address Registers (SAR n )
5
Table 16-10. SAR n Field Descriptions
6
Figure
7
All zeros
16-11, contain the transaction attributes for the DMA
All zeros
SAD
Description
8
11
12
15 16
Access: Read/Write
—
Access: Read/Write
DMA Controller
27 28
16-17
EDAD
31
31