MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1191

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

19.5.1.8
Whether low-power modes are automatically re-enabled after an interrupt is processed differs depending
on whether the low power mode was entered due to a write to the core MSR[WE] bit or the low power
mode was entered due to a write to POWMGTCSR.
19.5.1.8.1
When an interrupt is asserted to the CPU, the core complex saves portions of the MSR to MCSRR1,
CSRR1, or SRR1 (depending on the type of interrupt), and restores those values on return from the routine.
MSR[WE], which gates the doze, nap, and sleep power management outputs (internal device signals) from
the core complex, is always among the bits saved and restored; hence these outputs negate to the
MPC8533E power management logic when the interrupt begins processing in the core. They return to their
previous state when the core executes an rfi, rfci, or rfmci instruction.
Processor
19.5.1.8.2
The IRQ_MSK and CI_MSK fields of the POWMGTCSR register prevent int interrupts or cint critical
interrupts from waking the device from a low power state. This is true regardless of the method used to
enter the low power state.
Any unmasked interrupt (not masked by the mask bits in the POWMGTCSR register) causes the
POWMGTCSR[DOZ,SLP] fields to be cleared when it occurs. When such an interrupt occurs, the device
returns to the normal operating mode and does not automatically attempt to return to a low power state
after the interrupt is handled.
Note that interrupts caused by the unconditional debug event (UDE) and machine check (MCP) signals are
not masked by the IRQ_MSK and CI_MSK fields; therefore, when these signals assert, the
POWMGTCSR[DOZ,SLP] fields are cleared and the device will return to full power operation. See
Section 19.4.1.13, “Power Management Control and Status Register (POWMGTCSR),”
information about the bits of POWMGTCSR.
Note also that unmasked interrupts that occur while the device is in the process of going into the sleep state
(before sleep is completely attained) can also cause the device to clear the POWMGTCSR[DOZ,SLP]
fields and return the device to full power operation.
Freescale Semiconductor
Core,” lists interrupts that cause the MPC8533E to wake up.
Interrupts and Power Management
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Interrupts and Power Management Controlled by MSR[WE]
Returning doze, nap, and sleep signals to their original state when
MSR[WE] is restored differs from how power management is implemented
on earlier devices based on PowerPC ISA where MSR[POW], which
enables power-down requests, is cleared when the processor exits a
low-power state and is not automatically restored, as it is in Power ISA
implementations.
Interrupts and Power Management Controlled by POWMGTCSR
NOTE
Section 10.1.3, “Interrupts to the
for detailed
Global Utilities
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