MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1082

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI Express Interface Controller
18.3.6.3
The PCI Express error disable register, shown in
detect register’s bits.
Table 18-25
18-34
Offset 0xE10
Reset
Reset
Bits
1–7
W
W
R
R
10
11
12
13
14
0
8
9
CRSTD MISD IOISD CISD CIEPD IOIEPD OACD IOIAD
MED
16
0
CDNSCD Completion with data not successful disable. When set will disable the setting of
CRSNCD CRS non configuration disable. When set will disable the setting of PEX_ERR_DR[CRSNC] bit.
PCACD
ICCAD
PNMD
Name
PCTD
MED
describes the fields of the PCI Express error disable register.
PCI Express Error Disable Register (PEX_ERR_DISR)
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
17
1
Figure 18-26. PCI Express Error Disable Register (PEX_ERR_DISR)
Table 18-25. PCI Express Error Disable Register Field Descriptions
Multiple errors disable. When set will disable the setting of PEX_ERR_DR[ME] bit.
1 Disable multiple errors detection
0 Enable multiple errors detection
Reserved
PCI Express completion time-out disable. When set will disable the setting of PEX_ERR_DR[PET]
bit.
1 Disable PCI Express completion time-out detection
0 Enable PCI Express completion time-out detection
Reserved
PCI Express CA completion disable. When set will disable the setting of PEX_ERR_DR[PCAC] bit.
1 Disable completion with CA status detection
0 Enable completion with CA status detection
PCI Express no map disable. When set will disable the setting of PEX_ERR_DR[PNM] bit.
1 Disable no map PCI Express packet detection
0 Enable no map PCI Express packet detection
PEX_ERR_DR[CDNSC] bit.
1 Disable completion with data not successful detection
0 Enable completion with data not successful detection
1 Disable CRS non configuration detection
0 Enable CRS non configuration detection
Invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA configuration access disable. When set will
disable the setting of PEX_ERR_DR[ICCA] bit.
1 Disable invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access detection
0 Enable invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access detection
18
19
20
—
21
22
Figure
23
7
All zeros
All zeros
PCTD
18-26, controls the setting of the PCI Express error
24
8
Description
—
9
PCACD PNMD CDNSCD CRSNCD ICCAD IACAD
10
11
—
12
Freescale Semiconductor
13
Access: Read/Write
14
15
31