MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 530

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
Table 12-27
12-52
Address MDEU 0x3_6000
The following bits are described for information only. They are not under direct user control.
The following bits are controlled through the MODE0 or MODE1 fields of the descriptor header.
62–63
0–52
Bits
Bits
53
54
55
56
60
61
Reset
W
R
NEW=1 Determines the configuration of the MDEU mode register. This table shows the configuration for NEW=1.
HMAC Specifies whether to perform an HMAC operation:
CONT
Name
Name
0
STIB
ALG
PD
—
—
describes MDEU mode register fields in the new configuration.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 12-26. MDEU Mode Register in Old Configuration (NEW = 0) (continued)
Reserved
SSL/TLS inbound, block cipher.
0 Normal operation.
1 Special operation only for SSL/TLS inbound, block cipher. Upon receiving an EU_Go indication, the MDEU
Reserved. Must be set to zero.
Continue. Most operations will require this bit to be cleared. Set only when the data to be hashed is spread
across multiple descriptors.
0 Perform autopadding and complete the message digest. Used when the entire hash is performed with one
1 This hash will be continued in a subsequent descriptor. Do not autopad and do not complete the message
0 Normal operation
1 Perform an HMAC operation. This requires a key and key length. If this is set then the SMAC bit should be
If set, configures the MDEU to automatically pad partial message blocks.This bit must be programmed
opposite to the CONT bit.
0 Do not autopad.
1 Perform automatic message padding whenever an incomplete message block is detected.
Message digest algorithm selection
00 SHA-160 algorithm (full name for SHA-1)
01 SHA-256 algorithm
10 MD5 algorithm
11 SHA-224 algorithm
performs a calculation involving the last valid byte of data written into its input FIFO (which is pad length) to
compute a final data size. The MDEU then processes the amount of data specified by this data size, and
completes the message digest.
descriptor, or on the last of a sequence of descriptors.
digest.
0.
Figure 12-30. MDEU Mode Register in New Configuration (NEW = 1)
Table 12-27. MDEU Mode Register in New Configuration (NEW = 1)
—
52
STIB NEW — CONT CICV SMAC INIT HMAC EALG ALG
53
All zeros
Description
Description
54
55
56
57
58
59
Freescale Semiconductor
Access: Read/Write
60
61
62 63