MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 735

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
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If configured in half-duplex mode (10- and 100-Mbps operation; MACCFG2[Full Duplex] is
cleared), the MAC complies with the IEEE CSMA/CD access method.
If configured in full-duplex mode (10/100/1000 Mbps operation; MACCFG2[Full Duplex] is set),
the MAC supports flow control. If flow control is enabled, it allows the MAC to receive or send
PAUSE frames.
10- and 100-Mbps MII interface operation
The MAC–PHY interface operates in MII mode by setting MACCFG2[I/F Mode] = 01. The MII
is the media-independent interface defined by the 802.3 standard for 10/100 Mbps operation. The
speed of operation is determined by the TSECn_TX_CLK and TSECn_RX_CLK signals, which
are driven by the transceiver. The transceiver either auto-negotiates the speed, or it may be
controlled by software using the serial management interface (MDC/MDIO signals) to the
transceiver.
Clause 22.2.4 of the IEEE 802.3 specification describes the MII management interface.
10- and 100-Mbps RMII interface operation
The RMII is the reduced media-independent interface defined by the RMII Consortium (March
1998) for 10/100 Mbps operation. The speed of operation is determined by the TSECn_TX_CLK
signal, which is driven by the transceiver.
1000 Mbps GMII and TBI interface operation
The MAC–PHY interface operates in GMII mode by setting MACCFG2[I/F Mode] = 10. The
GMII is the gigabit media-independent interface defined by the 802.3 standard for 1000-Mbps
operation.
Independently, the MAC-PHY interface can also operate in TBI mode. Note that either the TBI or
GMII interface is chosen, not both at the same time. TBI is the 10-bit interface which contains PCS
functions (10-bit encoding/decoding) as defined by the 802.3 standard.
In reduced-pin count mode (RGMII or RTBI), the MAC remains configured in GMII or TBI but
the eTSEC muxes and decodes the input signals and provides the MAC with the expected interface.
eTSEC provides the TSECn_GTX_CLK to the PHY in either GMII or TBI mode of operation.
MAC address recognition options
The options supported are promiscuous, broadcast, exact unicast address match, exact unicast
virtual address match to support router redundancy, and multicast hash match. For detailed
descriptions refer to
eTSEC supports automatic LAN-initiated wake-up during power management via the AMD Magic
Packet™ protocol, as described in
Receive frame parsing options
Frame parsing options are to disable parsing (no TCP/IP off-load), IP header parsing, and TCP or
UDP parsing. Parsing must be enabled to make use of receive queue filing algorithms. The options
are detailed in
Receive queue selection options
Received frames are by default sent to a single buffer descriptor ring. If multiple receive queues
are enabled, a receive queue filer can be programmed with selection criteria to differentiate
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Section 15.6.4, “TCP/IP Off-Load.”
Section 15.6.3.7, “Frame Recognition.”
Section 15.6.3.8, “Magic Packet Mode.”
Enhanced Three-Speed Ethernet Controllers
15-5