MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 987

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
PCI_REQ[4:0]
PCI_PERR
PCI_PAR
Signal
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 17-2. PCI Interface Signals—Detailed Signal Descriptions (continued)
I/O
I/O PCI parity. The PCI parity signal is both an input and output signal on this PCI controller.
I/O PCI parity error. The PCI parity error signal is both an input and output signal on this PCI controller.
O As outputs for the bidirectional PCI parity, these signals operate as described below.
O As outputs for the bidirectional PCI parity error, these signals operate as described below.
I As inputs for the bidirectional PCI parity, these signals operate as described below.
I As inputs for the bidirectional PCI parity error, these signals operate as described below.
I PCI bus request
disabled, PCI_REQ[0] is an output. Note that PCI_REQ[ n ] is a point-to-point signal. Every master has
its own bus request signal. Following is the state meaning for the PCI_REQ[ n ] input.
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
State
State
State
State
State
Asserted—Indicates odd parity across the PCI_AD[31:0] and PCI_C/BE[3:0] signals during
Negated—Indicates even parity across the PCI_AD[31:0] and PCI_C/BE[3:0] signals
Asserted—Indicates odd parity driven by another PCI master or the PCI target during read
Negated—Indicates even parity driven by another PCI master or the PCI target during read
Asserted—Indicates that this PCI controller, acting as a PCI agent, detected a data parity
Negated—Indicates no error.
Asserted—Indicates that another PCI agent detected a data parity error while this PCI
Negated—Indicates no error.
Asserted—Indicates that agent n is requesting control of the PCI bus to perform a
Negated—Indicates that agent n does not require use of the PCI bus.
.
address and data phases.
during address and data phases.
data phases.
data phases.
error. (The PCI initiator drives PCI_PERR on read operations; the PCI target drives
PCI_PERR on write operations.)
controller was sourcing data (this PCI controller was acting as the PCI initiator during
a write, or was acting as the PCI target during a read).
transaction.
Input signals on this PCI controller when the arbiter is enabled. When the arbiter is
Description
PCI Bus Interface
17-9