MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 59

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

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Freescale Semiconductor
8-Bit Encoded Packet FIFO Timing ................................................................................. 15-140
Definition of Custom Preamble Sequence ........................................................................ 15-146
Definition of Received Preamble Sequence...................................................................... 15-147
Ethernet Address Recognition Flowchart ......................................................................... 15-148
Sample C Code for Computing eTSEC Hash Table Indices............................................. 15-150
Location of Frame Control Blocks for TOE Parameters .................................................. 15-158
Transmit Frame Control Block ......................................................................................... 15-158
Receive Frame Control Block........................................................................................... 15-160
Structure of the Receive Queue Filer Table ...................................................................... 15-163
Example of eTSEC Memory Structure for BDs ............................................................... 15-174
Buffer Descriptor Ring...................................................................................................... 15-174
Transmit Buffer Descriptor ............................................................................................... 15-175
Mapping of TxBDs to a C Data Structure......................................................................... 15-175
Receive Buffer Descriptor................................................................................................. 15-178
Mapping of RxBDs to a C Data Structure ........................................................................ 15-179
DMA Block Diagram............................................................................................................ 16-1
DMA Operational Flow Chart .............................................................................................. 16-4
DMA Signal Summary.......................................................................................................... 16-5
DMA Mode Registers (MRn) ............................................................................................. 16-10
Status Registers (SRn)......................................................................................................... 16-12
Basic Chaining Mode Flow Chart....................................................................................... 16-14
Extended Current Link Descriptor Address Registers (ECLNDARn) ............................... 16-14
Current Link Descriptor Address Registers (CLNDARn) .................................................. 16-15
Source Attributes Registers (SATRn) ................................................................................. 16-16
Source Address Registers (SARn) ...................................................................................... 16-17
Destination Attributes Registers (DATRn) ......................................................................... 16-17
Destination Address Registers (DARn) .............................................................................. 16-19
Byte Count Registers (BCRn)............................................................................................. 16-19
Next Link Descriptor Address Registers (NLNDARn) ...................................................... 16-20
Extended Next Link Descriptor Address Registers (ENLNDARn).................................... 16-20
Extended Current List Descriptor Address Registers (ECLSDARn) ................................. 16-21
Current List Descriptor Address Registers (CLSDARn) .................................................... 16-21
Extended Next List Descriptor Address Registers (ENLSDARn)...................................... 16-22
Next List Descriptor Address Registers (NLSDARn) ........................................................ 16-22
Source Stride Registers (SSRn) .......................................................................................... 16-23
Destination Stride Registers (DSRn) .................................................................................. 16-23
DMA General Status Register (DGSR) .............................................................................. 16-24
External Control Interface Timing ...................................................................................... 16-31
Stride Size and Stride Distance ........................................................................................... 16-33
DMA Transaction Flow with DMA Descriptors ................................................................ 16-36
List Descriptor Format ........................................................................................................ 16-37
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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