MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1066

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI Express Interface Controller
The fields of the PCI Express power management command register are described in
18.3.4
18.3.4.1
The IP block revision register 1 is shown in
Table 18-13
18-18
Offset 0xBF8
Reset 0
16–23
24–31
0–28
0–15
Bits
Bits
29
30
31
W
R
0
IP_MN Block Minor Revision
IP_MJ Block Major Revision
SPMES Set PME status. This will set the PME status bit and if PME is enabled (see
PTOMR PME_Turn_Off message request. When set will broadcast a PME turn_off message. This bit should not be
Name
IP_ID
EXL2S
Name
0
—
PCI Express IP Block Revision Registers
contains descriptions of the fields of the IP block revision register 1.
0
IP Block Revision Register 1 (PEX_IP_BLK_REV1)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Block ID
0
Table 18-13. PCI Express IP Block Revision Register 1 Field Descriptions
Reserved
Express Power Management Status and Control Register—0x48,” on page 18-69
will transmit a PM_PME message upstream. This bit should not be used when in RC mode. This bit is
self-clearing.
Exit L2 state. When set will exit the link state out of L2/L3 ready state in order to send new requests. The
request is only made when entered_L2/L3 ready state is active. This bit is self-clearing. When the link has
exited L2/L3 ready state, the status bit Exit_L2/L3 ready state will be set. This bit should not be used when
in EP mode.
used when in EP mode. This bit is self-clearing
0
0
1
IP_ID
0
Table 18-12. PEX_PMCR Field Descriptions
0
Figure 18-11. IP Block Revision Register 1
0
0
0
1
Figure
0
0
18-11.
15 16
0
Description
Description
0
0
0
IP_MJ
0
0
0
0
23 24
1
Section 18.3.9.3, “PCI
0
Freescale Semiconductor
0
for more information) it
Table
0
Access: Read-only
IP_MN
0
18-12.
0
0
0
31
0