MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 111

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

1.3.3
When the on-chip memory is configured as an SRAM, the memory can be configured to reside at any
aligned location in the memory map. It is byte-accessible, and fully ECC protected using
read-modify-write transactions for sub-cache-line transactions. I/O devices can access the SRAM by
marking transactions global so that they are directed to the CCB.
1.3.4
The on-chip memory arrays include a 256-Kbyte data array, an address tag array, and a status array.
The data array is organized as 1024 sets of eight cache lines. Each cache line size is 32 bytes. The
replacement policy within each eight-way set is governed by a pseudo-LRU algorithm. The data is
protected with ECC and the tag array is protected by parity.
The L2 cache tags are non-blocking for efficient load/store and snooping operations. The L2 cache can be
accessed internally while a load miss is pending (allowing hits under misses). Subsequent to a load miss
updating the memory, loads or stores can occur to that line on the very next cycle.
The L2 status array maintains status bits for each line that are used to determine the status of the line.
Different combinations of these bits result in different L2 states. Note that because the cache is always
write-through, there is no modified state. The status bits include:
All accesses to the L2 memory are fully pipelined so back-to-back loads and stores can have single-cycle
throughput.
The cache can be configured to allocate instructions only, data only, or both. It can also be configured to
allocate global I/O writes that correspond to a programmable address window or that use a special
transaction type (stashing). In this way, DMA engines or I/O devices can force data into the cache.
Freescale Semiconductor
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— Tag parity (1 bit covering all tag bits)
— Cache mode supports instruction caching, data caching, or both.
— External masters can force data to be allocated into the cache through programmed memory
— Separate locking for instructions and data so that locks can be set and cleared separately
— Supports locking the entire cache or selected lines
— Flash clearing done through writes to L2 configuration registers
— Locks for the entire cache may be set and cleared by accesses to memory-mapped control
V—Valid
IL—Instruction locked
DL—Data locked
ranges or special transaction types.
– Individual line locks are set and cleared through core-initiated instructions, by external
registers.
On-Chip Memory as Memory-Mapped SRAM
On-Chip Memory as L2 Cache
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
reads or writes, or by accesses to programmed memory ranges.
Overview
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