MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 110

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Overview
1.3.2
The MPC8533E contains an internal 256-Kbyte memory array that can be configured as memory-mapped
SRAM or as a look-aside L2 cache. The array can also be divided into two arrays, one of which may be
used as cache and the other as SRAM.
The memory controller for this array connects to the core complex bus (CCB) and communicates via
128-bit read and write buses to the e500 core and theMPC8533E system logic.
The on-chip memory unit contains:
1-12
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•
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— Instruction L1 MMU
— Unified L2 MMU
— Software reload for TLBs
— Support for as much as 4 Gbytes (2
— Support for as much as 64 Gbytes (2
— Support for big-endian and true little-endian memory on a per-page basis
Power management
— Dynamic power management on the core minimizes power consumption of functional units,
— Core power-saving modes: core-halted and core-stopped
— NAP, DOZE, and SLEEP bits in HID0 that can be used to assert nap, doze, and sleep core
Testability
— LSSD scan design
— JTAG interface
— ESP support
256 Kbytes of on-chip memory
— L2 cache partitioning is configurable
— SRAM operation is byte-accessible.
— Data ECC on 64-bit boundaries (single-error correction, double-error detection)
– 64-entry, four-way set-associative TLB for 4-Kbyte pages
– Four-entry, four-way set-associative TLB for 4-Kbyte pages
– 16-entry, fully-associative TLB array for variable-sized pages
– 512-entry, four-way set-associative TLB for 4-Kbyte pages
such as execution units, caches, and MMUs, when they are idle.
output signals to initiate power-saving modes at the integrated device level.
– Can act as a 256-Kbyte L2 cache
– Array can be partitioned into either L2 cache or memory mapped SRAM on a 1-, 2-, 4-, or
– Stashing of I/O data into the L2 array is supported, but can be limited to a 1-, 2-, or 4-way
On-Chip Memory Unit
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
– 256-Kbyte array organized as 1024 eight-way sets of 32-byte cache lines
8-way basis
basis
32
36
) of virtual memory
) of physical memory
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