MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 447

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

10.4.2
A processor servicing an interrupt, can be interrupted again only if the PIC receives an interrupt request
from a source with higher priority than the one being serviced. This is true even if software, as part of its
interrupt service routine, writes a new and lower value into the CTPR.
Thus, although several interrupts may be in-service simultaneously, the code currently executing is always
handling the highest priority of all the interrupts that are in service. When the processor performs an EOI
cycle, this highest priority interrupt is taken out-of-service. The next EOI cycle takes the next-highest
priority interrupt out-of-service, and so on. An interrupt with lower priority than those currently in-service
is not started until all higher priority interrupts complete even if its priority is greater than the CTPR value.
10.4.3
Under certain circumstances, the PIC has no valid vector to return to the processor during an interrupt
acknowledge cycle. In these cases, the spurious vector from the spurious vector register is returned. The
following cases cause a spurious vector fetch:
In all cases, a spurious vector is not returned if there is another pending interrupt that has sufficient priority
to interrupt the processor. If such an interrupt is available, the vector for that interrupt source is returned.
The EOI register should not be written in response to the spurious vector. Otherwise, a previously-accepted
interrupt might be cleared unintentionally.
10.4.4
There are four 32-bit message registers that can be used to send 32-bit messages to the processor. A
messaging interrupt is generated by writing a message register if the corresponding enable bit in the
message enable/status register is set, and the interrupt is not masked. Reading the message register or
writing a 1 to the status bit clears the interrupt.
10.4.5
There are eight shared MSIRs, described in
Registers
interrupts. Up to 32 sources can share any individual MSI register. A shared message signaled interrupt is
generated by writing to Shared Message Signaled Interrupt Index Register (MSIIR) fields SRS and IBS.
This register is primarily intended to support inbound PCI Express message signaled interrupts (MSIs)
when the PCI Express controller is configured as a root complex (RC).
Freescale Semiconductor
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int is asserted in response to an externally sourced interrupt which is activated with level-sensitive
logic, and the asserted level is negated before the interrupt is acknowledged.
int is asserted for an interrupt source that is later masked (using the mask bit in the vector/priority
register corresponding to that source) before the interrupt is acknowledged.
int is asserted for an interrupt source that is later masked by an increase in the task priority level
before the interrupt is acknowledged.
An interrupt acknowledge cycle is performed by the processor in spite of the fact that the int signal
has not been asserted by the PIC.
(MSIRs),” that indicate which of the interrupt sources sharing the MSI register have pending
Shared Message Signaled Interrupts
Nesting of Interrupts
Spurious Vector Generation
Messaging Interrupts
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Section 10.3.6.1, “Shared Message Signaled Interrupt
Programmable Interrupt Controller
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