MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 377

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

The value of the above parameters (in whole clock cycles) must be set by boot code at system start-up (in
the TIMING_CFG_0, TIMING_CFG_1, TIMING_CFG_2, and TIMING_CFG_3 registers as described
in
SDRAM Timing Configuration 1 (TIMING_CFG_1),” Section 9.4.1.6, “DDR SDRAM Timing
Configuration 2 (TIMING_CFG_2),”
(TIMING_CFG_3),”) and be kept in the DDR memory controller configuration register space.
The following figures show SDRAM timing for various types of accesses. System software is responsible
(at reset) for optimally configuring SDRAM timing parameters. The programmable timing parameters
apply to both read and write timing configuration. The configuration process must be completed and the
DDR SDRAM initialized before any accesses to SDRAM are attempted.
Figure 9-37
for a single-beat read operation,
burst-write operation. Note that all signal transitions occur on the rising edge of the memory bus clock and
that single-beat read operations are identical to burst-reads. These figures assume the CLK_ADJUST is
set to 1/2 DRAM cycle, an additive latency of 0 DRAM cycles is used, and the write latency is 1 DRAM
cycle (for DDR1).
Freescale Semiconductor
WR_DATA_DELAY
Timing Intervals
Section 9.4.1.4, “DDR SDRAM Timing Configuration 0 (TIMING_CFG_0),” Section 9.4.1.5, “DDR
WRTORD
REFREC
WRREC
REFINT
through
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Refresh interval. Represents the number of memory bus clock cycles between refresh cycles.
Depending on DDR_SDRAM_CFG_2[NUM_PR], some number of rows are refreshed in each SDRAM
bank during each refresh cycle. The value of REFINT depends on the specific SDRAMs used and the
frequency of the interface as t
be calculated by referring to the AC specification of the SDRAM device. The AC specification indicates
a maximum refresh to activate interval in nanoseconds.
Provides different options for the timing between a write command and the write data strobe. This allows
write data to be sent later than the nominal time to meet the SDRAM timing requirement between the
registration of a write command and the reception of a data strobe associated with the write command.
The specification dictates that the data strobe may not be received earlier than 75% of a cycle, or later
than 125% of a cycle, from the registration of a write command. This parameter is not defined in the
SDRAM specification. It is implementation-specific, defined for the DDR memory controller in
TIMING_CFG_2.
The number of clock cycles from the last beat of a write until a precharge command is allowed. This
interval, write recovery time, is listed in the AC specifications of the SDRAM as t
Last write pair to read command. Controls the number of clock cycles from the last write data pair to the
subsequent read command to the same bank as t
The number of clock cycles from the refresh command until an activate command is allowed. This can
Figure 9-40
Table 9-47. DDR SDRAM Interface Timing Intervals (continued)
Figure 9-38
show DDR SDRAM timing for various types of accesses; see
and
Section 9.4.1.3, “DDR SDRAM Timing Configuration 3
RP
for a single-beat write operation, and
.
Definition
WTR
.
Figure 9-40
WR
DDR Memory Controller
.
Figure 9-37
for a
9-55