MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 387

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Page mode can dramatically reduce access latencies for page hits. Depending on the memory system
design and timing parameters, using page mode can save two to three clock cycles for subsequent burst
accesses that hit in an active page. Also, better performance can be obtained by using more banks,
especially in systems which use many different channels. Page mode is disabled by clearing
DDR_SDRAM_INTERVAL[BSTOPRE] or setting CSn_CONFIG[AP_nEN].
9.5.11
The DDR memory controller supports error checking and correcting (ECC) for the data path between the
core master and system memory. The memory detects all double-bit errors, detects all multi-bit errors
within a nibble, and corrects all single-bit errors. Other errors may be detected, but are not guaranteed to
be corrected or detected. Multiple-bit errors are always reported when error reporting is enabled. When a
single-bit error occurs, the single-bit error counter register is incremented, and its value compared to the
single-bit error trigger register. An error is reported when these values are equal. The single-bit error
registers can be programmed such that minor memory faults are corrected and ignored, but a catastrophic
memory failure generates an interrupt.
For writes that are smaller than 64 bits, the DDR memory controller performs a double-word read from
system memory of the address for the write (checking for errors), and merges the write data with the data
read from memory. Then, a new ECC code is generated for the merged double word. The data and ECC
code is then written to memory. If a multi-bit error is detected on the read, the transaction completes the
read-modify-write to keep the DDR memory controller from hanging. However, the corrupt data is masked
on the write, so the original contents in SDRAM remain unchanged.
The syndrome encodings for the ECC code are shown in
Freescale Semiconductor
Data
Bit
10
11
12
13
0
1
2
3
4
5
6
7
8
9
Error Checking and Correcting (ECC)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
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Syndrome Bit
Table 9-50. DDR SDRAM ECC Syndrome Encoding
3
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4
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5
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Table 9-50
Data
Bit
32
33
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38
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42
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45
0
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and
1
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Table
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Syndrome Bit
9-51.
3
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DDR Memory Controller
5
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6
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7
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9-65