MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1177

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

19.4.1.14 Machine Check Summary Register (MCPSUMR)
Shown in
check interrupt. All MCPSUMR bits function as write-1-to-clear.
Note that other conditions can cause a machine check condition not summarized in MCPSUMR. For
example, uncorrectable read errors cause the assertion of core_fault_in, which may directly cause a
machine check (if HID1[RFXE] = 1). If RFXE = 0, the assertion of core_fault_in does not directly cause
a machine check interrupt, but must be handled by the block that generated the error. For more information
about RFXE, see
Freescale Semiconductor
Offset 0xE_0090
Reset
15–27
Bits
14
28
29
30
31
W
R
0
NAPPING Nap status
DOZING Doze status
SLPING
Name
SLP
Figure
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Register fields designated as write-1-to-clear are cleared only by writing
ones to them. Writing zeros to them has no effect.
Sleep mode
19-14, MCPSUMR contains bits summarizing some of the sources of a pending machine
0 No request to put device in sleep mode.
1 Device is to be placed in sleep mode. Instruction fetching is halted, snooping of L1 caches is disabled,
Reserved
0 Device is not in doze mode.
1 The MPC8533E is in doze mode because POWMGTCSR[DOZ] is set or because HID0[DOZE] and
0 Device is not in nap mode.
1 The MPC8533E is in nap mode because HID0[NAP] and MSR[WE] are set. The core has halted
Sleep status
0 Device is not attempting to reach sleep mode.
1 The device is attempting to SLEEP because POWMGTCSR[SLP] is set or because HID0[SLEEP] and
Reserved. Should be cleared.
Section 6.10.2, “Hardware Implementation-Dependent Register 1 (HID1).”
and most functional blocks are shut down in both the e500 core and the system logic.
MSR[WE] (in the e500 core) are set. The core has halted instruction fetching, but all other functional
blocks in the core and device are running.
instruction fetching, snooping of the L1 caches is disabled, and all of the core’s functional units except
the timer facilities are shut down. All functional blocks in the device are running.
MSR[WE] (in the e500 core) are set. Most functional blocks in the core and device are shut down or are
attempting to shut down.
Figure 19-14. Machine Check Summary Register (MCPSUMR)
Table 19-16. POWMGTCSR Field Descriptions (continued)
—
NOTE
All zeros
Description
28
WRS SRESET MCP_IN
w1c
29
w1c
30
Global Utilities
Access: w1c
w1c
19-17
31