MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 780

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
15.5.3.3.2
The eTSEC writes to this register under the following conditions:
15-50
24–25
Bits
26
27
28
29
30
31
•
•
•
A frame interrupt event occurred on one or more RxBD rings
The receiver runs out of descriptors due to a busy condition on a RxBD ring
The receiver was halted because an error condition was encountered while receiving a frame
PRSDEP Parser control. The level of parser layer recognition is determined as follows:
BC_REJ
PROM
EMEN
Name
RSF
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Receive Status Register (RSTAT)
00 Parser disabled. Receive frame filer must also be disabled by clearing RCTRL[FILREN]. This should
01 Only L2 (ethernet) protocols are recognized. For packets received over FIFO interface, this parse level
10 L2 and L3 (IP) protocols are recognized. This is the minimum parse level for IP packets received over
11 L2, L3 and L4 (TCP/UDP) protocols are recognized.
If this field is non-zero, a TOE frame control block is prepended to the received frame, and the first RxBD
will point to the FCB.
Note that if PRSDEP is cleared, VLEX must be cleared as well. (VLAN tag extraction is only supported
when the parser is enabled.) Also, if PRSDEP is cleared, FILREN must also be cleared.
Reserved
Broadcast frame reject. If this bit is set, frames with DA (destination address) = FFFF_FFFF_FFFF are
rejected unless RCTRL[PROM] is set. If both BC_REJ and RCTRL[PROM] are set, then frames with
broadcast DA are accepted and the M (MISS) bit is set in the receive BD.
Promiscuous mode. All Ethernet frames, regardless of destination address, are accepted.
Receive short frame mode. When set, enables the reception of frames shorter than 64 bytes. For packets
received over the FIFO packet interface, this bit has no effect (packets shorter than 64 bytes are always
accepted).
0 Ethernet frames less than 64B in length are silently dropped.
1 Frames more than 16B and less than 64B in length are accepted upon a DA match.
Note that frames less than or equal to 16B in length are always silently dropped.
Exact match MAC address enable. If this bit is set, the MAC01ADDR1–MAC15ADDR1 and
MAC01ADDR2–MAC15ADDR2 registers are recognized as containing MAC addresses aliasing the
MAC’s station address. Setting this bit therefore allows eTSEC to receive Ethernet frames having a
destination address matching one of these 15 addresses.
Reserved
be the setting for raw (non-IP) packets received over FIFO interface
is unavailable.
FIFO interface.
Table 15-26. RCTRL Field Descriptions (continued)
Description
Freescale Semiconductor