MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1327

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Index
Freescale Semiconductor
DUART
eTSEC
global utilities
I
JTAG
LBC
2
C
UART_CTS[0:1] (DUART clear to send), 13-1, 13-3
UART_RTS[0:1] (DUART request to send), 13-1, 13-3,
UART_SIN [0:1] (DUART transmitter serial data in),
UART_SOUT [0:1] (DUART transmitter serial data
EC_GTX_CLK125 (eTSEC gigabit transmit 125 MHz
EC_MDC (eTSEC management data clock), 15-10
EC_MDIO (eTSEC management data input/output,
FIFO interface signal summary, 15-140
TSECn_COL (eTSEC 1–4 collision input), 15-9
TSECn_CRS (eTSEC 1–4 carrier sense input/FIFO
TSECn_GTX_CLK (eTSEC 1–4 gigabit transmit clock),
TSECn_RX_CLK (eTSEC 1–4 receive clock), 15-10
TSECn_RX_DV (eTSEC 1–4 receive data valid), 15-10
TSECn_RX_ER (eTSEC 1–4 receive error), 15-11
TSECn_RXD[7:0] (eTSEC 1–4 receive data in), 15-11
TSECn_TX_CLK (eTSEC 1–4 transmit clock in), 15-11
TSECn_TX_EN (eTSEC 1–4 transmit data valid), 15-12
TSECn_TX_ER (eTSEC 1–4 transmit error), 15-12
TSECn_TXD[7:0] (eTSEC 1–4 transmit data out), 15-12
ASLEEP, 19-2, 19-28
CKSTP_IN (checkstop in), 19-2
CKSTP_OUT (checkstop out), 19-3
CLK_OUT, 19-3, 19-23
GPOUT[24:31], 19-3
SCL (serial clock), 11-3, 11-4
SDA (serial data), 11-3, 11-4
TCK (JTAG test clock), 21-8
TDI (JTAG test data input), 21-8
TDO (JTAG test data output), 21-8
TMS (JTAG test mode select), 21-8
TRST (JTAG test reset), 21-9
LA[27:31] (non-multiplexed address), 14-7
LAD[0:31] (multiplexed address/data), 14-7
LALE (external address latch enable), 14-5, 14-33
LBCTL (data buffer control), 14-7, 14-35
LBS[0:3] (UPM byte select), 14-6
LCK[0:2] (clock), 14-8
LCKE (clock enable), 14-7
LCS[0:7] (chip select), 14-5
13-4
13-2, 13-3
out), 13-2, 13-3
source), 15-10
BIDI), 15-10
receiver flow control), 15-9
15-9
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
other
PCI Express
PCI/PCI-X
PIC
reset
LCS0 (LBC chip select 0), 14-46
LDP[0:3] (data parity), 14-7, 14-36
LGPL0 (GP line 0), 14-6
LGPL1 (GP line 1), 14-6
LGPL2 (GP line 2), 14-6
LGPL3 (GP line 3), 14-6
LGPL4 (GP line 4), 14-6
LGPL5 (GP line 5), 14-7
LGTA (GPCM transfer acknowledge), 14-6, 14-46
LOE (GPCM output enable), 14-6
LPBSE (parity byte select), 14-6
LSDA10 (SDRAM A10), 14-6
LSDCAS (SDRAM CAS), 14-6
LSDDQM[0:3] (SDRAM data mask), 14-6
LSDRAS (SDRAM RAS), 14-6
LSDWE (SDRAM write enable), 14-6
LSYNC_IN (PLL synchronization in), 14-8
LSYNC_OUT (PLL synchronization out), 14-8
LWE[0:3] (GPCM write enable), 14-6
MDVAL (debug mode data valid), 4-20, 14-8, 21-3, 21-6
MSRCID[0:4] (debug source ID), 4-20, 14-8, 21-3, 21-7
TA (data transfer acknowledge), 14-34
UPWAIT (UPM wait), 14-6, 14-59
TEST_SEL (factory test), 21-6
THERM[0:1] (thermal resistor access), 21-9
SD_RX[7:0]/SD_RX[7:0] (PCI Express serial data input
SD_TX[7:0]/SD_TX[7:0] (PCI Express serial data
PCI_AD[63:0] (address/data bus), 17-6
PCI_C/BE[7:0] (command/byte enable), 17-7, 17-46,
PCI_DEVSEL (device select), 17-7, 17-48
PCI_FRAME (frame), 17-7, 17-45
PCI_GNT[4:0] (bus grant), 17-8, 17-43
PCI_IDSEL (initialization device), 17-8
PCI_IRDY (intitiator ready), 17-8, 17-45
PCI_PAR (parity), 17-9
PCI_PERR (parity error), 17-9, 17-66
PCI_REQ[4:0] (bus request), 17-9, 17-42
PCI_SERR (system error), 17-10, 17-66
PCI_STOP (stop), 17-10, 17-49
PCI_TRDY (target ready), 17-10, 17-45
IRQ[0:11], 10-8
IRQ_OUT, 10-8, 10-27
MCP, 10-8
UDE, 10-8
and complement) signals, 18-5
output and complement) signals, 18-5
17-48, 17-49, 17-65
Index-19
S–S