MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 580

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
12.5.1.5
The descriptor buffers (DBs) consists of 8 dword registers (DBn[0–7]), and contain the current descriptor
being processed by the channel. These registers are read-only, since the descriptor is always fetched from
system memory.
The write of any valid pointer to the fetch FIFO will cause the channel to read 64 contiguous bytes
beginning at the fetch address into the descriptor buffer.
For more information about the fields in a descriptor, see
12.5.1.6
The link table buffer consists of 4 dword registers (LTB0–LTB3), and contains the link table (scatter or
gather) being processed by the channel, when scatter/gather is in use. These registers are read-only, since
the link table is always fetched from system memory.
Any descriptor length/pointer dword with the jump bit set will cause the channel to read 32 contiguous
bytes beginning at the pointer address into the link table buffer. Additionally, any link table entry with the
next bit set causes the channel to read 32 contiguous bytes into the link table buffer. As the data may not
be so scattered as to require 4 link table entries to gather it, automatically reading 32 bytes (4 link table
entries) is pre-fetching, and is done for performance reasons. Proper use of the return and next bits is
required to avoid problems arising from pre-fetching.
For more information about the fields in a link table, see
12-102
Address
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
0
Crypto-Channel 1–4 Descriptor Buffers [0–7] (DB n [0–7])
Link Table Buffer Registers (Scatter or Gather)—LTB0–3
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Length0
Length1
Length2
Length3
Length4
Length5
Length6
15
Channel_1 0x3_1180–0x3_11BF, Channel_2 0x3_1280–0x3_12BF,
Channel_3 0x3_1380–0x3_13BF, Channel_4 0x3_1480–0x3_14BF
J1
J2
J3
J4
J5
J6
J7
16
Figure 12-77. Descriptor Buffer Format
Header
17
Extent0
Extent1
Extent2
Extent3
Extent4
Extent5
Extent6
23
24
Section 12.3.4, “Link Table Format.”
Section 12.3.1, “Descriptor Structure.”
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31
32
Freescale Semiconductor
Reserved
Pointer0
Pointer1
Pointer2
Pointer3
Pointer4
Pointer5
Pointer6
63