MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 596

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DUART
13.1.2
The communication channel provides a full-duplex asynchronous receiver and transmitter using an
operating frequency derived from the CCB clock.
The transmitter accepts parallel data from a write to the transmitter holding register (UTHR). In FIFO
mode, the data is placed directly into an internal transmitter shift register of the transmitter FIFO. The
transmitter converts the data to a serial bit stream inserting the appropriate start, stop, and optional parity
bits. Finally, it outputs a composite serial data stream on the channel transmitter serial data output signal
(SOUT). The transmitter status may be polled or interrupt driven.
The receiver accepts serial data bits on the channel receiver serial data input signal (SIN), converts it to
parallel format, checks for a start bit, parity (if any), stop bits, and transfers the assembled character (with
start, stop, parity bits removed) from the receiver buffer (or FIFO) in response to a read of the UART’s
receiver buffer register (URBR). The receiver status may be polled or interrupt driven.
13-2
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Clear to send (CTS) and ready to send (RTS) modem control functions
Software-selectable serial interface data format (data length, parity, 1/1.5/2 STOP bit, baud rate)
Line and modem status registers
Line-break detection and generation
Internal diagnostic support, local loopback, and break functions
Prioritized interrupt reporting
Overrun, parity, and framing error detection
Address Bus
Modes of Operation
Data
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Control
int
CCB_clk
HRESET
Interrupt
Control
Control
Logic
Figure 13-1. UART Block Diagram
Baud Rate Generator
Transmit Buffer
Receive Buffer
16-Bit Counter/
Output Port
Input Port
Freescale Semiconductor
SIN
SOUT
CTS
RTS