MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 169

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Most POR configuration signals have internal pull-up resistors so that if the desired setting is high, there
is no need for a pull-up resistor on the board. Other POR configuration signals do not use pull-ups and
therefore must be pulled high or low. Refer to the MPC8533E Integrated Processor Hardware
Specifications for proper resistor values to be used for pulling POR configuration signals high or low.
This section describes the functions and modes configured by POR configuration signals. Note that many
reset configuration settings are accessible to software through the following read-only memory-mapped
registers described in
4.4.3.1
The system PLL inputs, shown in
platform clock used by the MPC8533E. The platform clock, also called the CCB clock, drives the L2
cache, the DDR SDRAM data rate, and the e500 core complex bus (CCB). There is no default value for
this PLL ratio; these signals must be pulled to the desired values. See
Frequency
widths and frequencies. Note that the values latched on these signals during POR are accessible in the
PORPLLSR (POR PLL status register), as described in
(PORPLLSR).”
Freescale Semiconductor
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POR PLL status register (PORPLLSR)
POR boot mode status register (PORBMSR)
POR I/O impedance status and control register (PORIMPSCR)
POR device status register (PORDEVSR)
POR debug mode status register (PORDBGMSR)
General-purpose POR configuration register (GPPORCR)—Reports the value on LAD[0:31]
during POR (can be used to external system configuration)
Requirements,” for optimal selection of this ratio with regard to available high-speed interface
System PLL Ratio
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
In the following tables, the binary value 0b0 represents a signal pulled down
to GND and a value of 0b1 represents a signal pulled up to V
of the sense of the functional signal name on the signal.
Chapter 19, “Global Utilities”:
Table
4-9, establish the clock ratio between the SYSCLK input and the
NOTE
Section 19.4.1.1, “POR PLL Status Register
Section 4.4.4.2.1, “Minimum
DD
, regardless
Reset, Clocking, and Initialization
4-11