MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 668

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
14.4.3.4
The SDRAM machine supports page-mode operation. Each time a page is activated on the SDRAM
device, the SDRAM machine stores its address in a page register. The page information, which the user
writes to the ORn register, is used along with the bank size to compare page bits of the address to the page
register each time a bus-cycle access is requested. If a match is found, together with a bank match, the bus
cycle is defined as a page hit. An open page is automatically closed by the SDRAM machine if the bus
becomes idle, unless ORn[PMSEL] = 1.
14.4.3.5
The LBC can manage at most four open pages (one page per SDRAM bank) for a single SDRAM device.
After a page is opened, it remains open unless:
14.4.3.6
The lower address bus bits are connected to the memory device’s address port with the memory controller
multiplexing the row/column and the internal bank select lines. The position of the bank select lines are
set according to LSDMR[BSMA].
down to the lower output address signals during activate and shifts the bank select bits up to the address
signals specified by LSDMR[BSMA], supporting page-based interleaving. The lsb of the logical row
address (An in
of 32, 16, and 8 bits, respectively).
14-50
•
•
•
•
The next access is to a page in a different SDRAM device, in which case all open pages on the
current device are closed with a PRECHARGE-ALL-BANKS command.
The next access is to a page in an SDRAM bank that has a different page open on it, in which case
the old page is closed with a PRECHARGE-SINGLE-BANK command.
The current SDRAM device requires refresh services, in which case all open pages on the current
device are closed with a PRECHARGE-ALL-BANKS command.
The bus becomes idle and ORn[PMSEL] = 0, in which case all open pages in the current device
are closed with a PRECHARGE-ALL-BANKS command.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure
Page Hit Checking
Page Management
SDRAM Address Multiplexing
14-35) is aligned with the connected lsb of LAD (bits 29, 30, and 31 for port sizes
Figure 14-35
shows how the SDRAM controller shifts the row address
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