MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 380

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DDR Memory Controller
9.5.5
The DDR memory controller transfers the mode register set commands to the SDRAM array, and it uses
the setting of TIMING_CFG_0[MRS_CYC] for the Mode Register Set cycle time.
Figure 9-42
code; the second corresponds to SDMODE. The Mode Register Set cycle time is set to 2 DRAM cycles.
9-58
MCK[0], MCK[0]
MCK[1], MCK[1]
MCK[2], MCK[2]
DDR SDRAM Mode-Set Command Timing
SDRAM Clock
shows the timing of the mode-set command. The first transfer corresponds to the ESDMODE
CS[0]
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 9-41. DDR SDRAM Clock Distribution Example for x8 DDR SDRAMs
MDQ n
MRAS
MCAS
MDQS
MBA n
MWE
MCS
MA n
Figure 9-42. DDR SDRAM Mode-Set Command Timing
Code
0x4
0
DDR
1
A[15:0], BA[2:0], MRAS, MCAS, MWE, CKE
Code
0x0
2
DQ[0:7], DQS[0], DM[0]
DQ[8:15], DQS[1], DM[1]
DQ[16:23], DQS[2], DM[2]
DQ[24:31], DQS[3], DM[3]
DQ[32:39], DQS[4], DM[4]
DQ[40:47], DQS[5], DM[5]
DQ[48:55], DQS[6], DM[6]
DQ[56:63], DQS[7], DM[7]
ECC[0:7], DQS[8], DM[8]
3
4
5
6
7
8
9
10
Freescale Semiconductor
11
CS[1]
MCK[3], MCK[3]
MCK[4], MCK[4]
MCK[5], MCK[5]
12