MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 641

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

14.3.1.8
The UPM refresh timer (LURT), shown in
selected a UPM machine and are refresh-enabled (MxMR[RFEN] = 1). Each time the timer expires, a
qualified bank generates a refresh request using the selected UPM. The qualified banks rotate their
requests.
Table 14-14
14.3.1.9
The SDRAM refresh timer (LSRT), shown in
that selected a SDRAM machine and are refresh-enabled (LSDMR[RFEN] = 1). Each time the timer
expires, all qualifying banks generate a bank staggering auto-refresh request using the SDRAM machine.
Freescale Semiconductor
8–31
Bits Name
0–7 LURT UPM refresh timer period. Determines, along with the timer prescaler (MRTPR), the timer period according to
Offset 0x0A0
Offset 0x0A4
Reset
Reset
—
W
W
R
R
describes LURT fields.
the following equation:
Example: For a 266-MHz system clock and a required service rate of 15.6 µs, given MRTPR[PTP] = 32, the
LURT value should be 128 decimal. 128/(266 MHz/32) = 15.4 µs, which is less than the required service period
of 15.6 µs.
Note that the reset value (0x00) sets the maximum period to 256 × MRTPR[PTP] system clock cycles.
Reserved
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
0
UPM Refresh Timer (LURT)
SDRAM Refresh Timer (LSRT)
LURT
LSRT
Figure 14-12. LSRT SDRAM Refresh Timer (LSRT)
Figure 14-11. UPM Refresh Timer (LURT)
7
7
Table 14-14. LURT Field Descriptions
8
8
Figure
TimerPeriod
Figure
14-11, generates a refresh request for all valid banks that
14-12, generates a refresh request for all valid banks
All zeros
All zeros
Description
=
--------------------------------------------- -
⎛
⎝
Fsystemclock
--------------------------------------- -
MRTPR PTP
LURT
[
—
—
]
⎞
⎠
Access: Read/Write
Access: Read/Write
Local Bus Controller
31
31
14-23