MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 446

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Programmable Interrupt Controller
The internal in-service register (ISR) tracks all in-service interrupts. An interrupt is considered in-service
from the time its vector is read (through an IACK cycle) until the end of interrupt (EOI) register is written,
generating what the PIC considers an EOI signal.
10.4.1.1
Each interrupt source is assigned a priority value through its corresponding vector/priority register. Priority
values range from 0 to 15, where 15 is the highest. Interrupts are delivered only when the priority of the
interrupt source is greater than the current task priority. Therefore setting a source priority to zero inhibits
that interrupt.
The PIC services simultaneous interrupts occurring with the same priority according to the following
order:
For example, if MSG0, MSG2, and IPI0 all have the same priority and receive simultaneous interrupts,
they are serviced in the following order:
10.4.1.2
The CTPR is set by system software to indicate the relative importance of the task running on the
processor. The processor does not receive interrupts with a priority level equal to or lower than its current
task priority. Therefore setting the current task priority to 15 for a particular processor prevents the delivery
of any interrupt to the processor.
10.4.1.3
The PIC unit notifies the processor core of an interrupt by asserting the int signal. When the processor core
acknowledges the interrupt request by reading the interrupt acknowledge register (IACK) in the PIC unit,
the PIC returns the 16-bit vector associated with the interrupt source to the processor. The interrupt is then
considered to be in-service, and remains in-service until the processor performs a write to the PIC unit end
of interrupt register (EOI). Writing to the EOI is referred to as an EOI cycle.
10-50
1. MSG0–MSG3
2. MSI0–MSI7
3. IPI0–IPI3
4. Timer 0–timer 3
5. IRQ[0:11]/PCI INTx
6. Internal 0–internal 31
1. MSG0
2. MSG2
3. IPI0
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Interrupt Source Priority
Processor Current Task Priority
Interrupt Acknowledge
Freescale Semiconductor