MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 260

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Core Register Summary
6-44
34–35
42–43
49–63
Bits
32
33
36
37
38
39
40
41
44
45
46
47
48
DAC1W
DAC2W
DAC1R
DAC2R
Name
TRAP
ICMP
MRR
IRPT
IAC1
IAC2
UDE
BRT
RET
IDE
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Imprecise debug event. Set if MSR[DE] = 0 and a debug event causes its respective DBSR bit to be set.
Functions as write-one-to-clear.
Unconditional debug event. Set if an unconditional debug event occurred. Functions as
write-one-to-clear. If UDE (level sensitive, active low) is asserted, DBSR[UDE] is affected as follows:
MSR[DE]DBCR0[IDM]Action
X 0 No action.
0 1 UDE is set.
1 1 UDE is set and a debug interrupt is taken.
Most recent reset. Functions as write-one-to-clear. Undefined at power-on. The e500 implements
HRESET as follows:
0x No hard reset occurred since this bit was last cleared by software.
1x The previous reset was a hard reset.
Instruction complete debug event. Set if an instruction completion debug event occurred and
DBCR0[ICMP] = 1. Functions as write-one-to-clear.
Branch taken debug event. Set if a branch taken debug event occurred (DBCR0[BRT] = 1). Functions as
write-one-to-clear.
Interrupt taken debug event. Set if an interrupt taken debug event occurred (DBCR0[IRPT] = 1).
Functions as write-one-to-clear.
Trap instruction debug event. Set if a trap Instruction debug event occurred (DBCR0[TRAP] = 1).
Functions as write-one-to-clear.
Instruction address compare 1 debug event. Set if an IAC1 debug event occurred (DBCR0[IAC1] = 1).
Functions as write-one-to-clear.
Instruction address compare 2 debug event. Set if an IAC2 debug event occurred (DBCR0[IAC2] = 1).
Functions as write-one-to-clear.
Reserved, should be cleared
Data address compare 1 read debug event. Set if a read-type DAC1 debug event occurred
(DBCR0[DAC1] = 10 or 11). Functions as write-one-to-clear.
Data address compare 1 write debug event. Set if a write-type DAC1 debug event occurred
(DBCR0[DAC1] = 01 or 11). Functions as write-one-to-clear.
Data address compare 2 read debug event.Set if a read-type DAC2 debug event occurred
(DBCR0[DAC2] = 10 or 11). Functions as write-one-to-clear.
Data address compare 2 write debug event. Set if a write-type DAC2 debug event occurred
(DBCR0[DAC2] = 01 or 11). Functions as write-one-to-clear.
Return debug event. Set if a return debug event occurred (DBCR0[RET] = 1). Functions as
write-one-to-clear.
Reserved, should be cleared.
Table 6-38. DBSR Field Descriptions
Description
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