MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 25

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Paragraph
Number
14.4.3.7.2
14.4.3.7.3
14.4.3.7.4
14.4.3.7.5
14.4.3.7.6
14.4.3.8
14.4.3.9
14.4.3.10
14.4.3.11
14.4.3.11.1
14.4.4
14.4.4.1
14.4.4.1.1
14.4.4.1.2
14.4.4.1.3
14.4.4.1.4
14.4.4.2
14.4.4.2.1
14.4.4.2.2
14.4.4.3
14.4.4.4
14.4.4.4.1
14.4.4.4.2
14.4.4.4.3
14.4.4.4.4
14.4.4.4.5
14.4.4.4.6
14.4.4.4.7
14.4.4.4.8
14.4.4.4.9
14.4.4.4.10
14.4.4.5
14.4.4.6
14.4.4.7
14.5
14.5.1
14.5.1.1
14.5.1.2
14.5.1.3
Freescale Semiconductor
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Initialization/Application Information ......................................................................... 14-79
User-Programmable Machines (UPMs)................................................................... 14-58
Interfacing to Peripherals......................................................................................... 14-79
SDRAM Interface Timing ................................................................................... 14-55
SDRAM Read/Write Transactions....................................................................... 14-57
SDRAM MODE-SET Command Timing............................................................ 14-57
SDRAM Refresh.................................................................................................. 14-57
UPM Requests ..................................................................................................... 14-59
Programming the UPMs ...................................................................................... 14-62
UPM Signal Timing............................................................................................. 14-64
RAM Array.......................................................................................................... 14-64
Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge ............ 14-72
Extended Hold Time on Read Accesses .............................................................. 14-73
Memory System Interface Example Using UPM ................................................ 14-73
Multiplexed Address/Data Bus and Non-Multiplexed Address Signals ............. 14-79
Peripheral Hierarchy on the Local Bus................................................................ 14-80
Peripheral Hierarchy on the Local Bus for Very High Bus Speeds..................... 14-80
Activate-to-Read/Write Interval ...................................................................... 14-52
Column Address to First Data Out—CAS Latency......................................... 14-53
Last Data In to Precharge—Write Recovery ................................................... 14-53
Refresh Recovery Interval (RFRC) ................................................................. 14-54
External Address and Command Buffers (BUFCMD).................................... 14-54
SDRAM Refresh Timing ................................................................................. 14-58
Memory Access Requests................................................................................ 14-60
UPM Refresh Timer Requests ......................................................................... 14-61
Software Requests—RUN Command ............................................................. 14-61
Exception Requests.......................................................................................... 14-62
UPM Programming Example (Two Sequential Writes to the
UPM Programming Example (Two Sequential Reads from the
RAM Words..................................................................................................... 14-65
Chip-Select Signal Timing (CSTn) ................................................................. 14-67
Byte Select Signal Timing (BSTn) .................................................................. 14-68
General-Purpose Signals (GnTn, GOn)........................................................... 14-69
Loop Control (LOOP) ..................................................................................... 14-69
Repeat Execution of Current RAM Word (REDO) ......................................... 14-69
Address Multiplexing (AMX) ......................................................................... 14-70
Data Valid and Data Sample Control (UTA) ................................................... 14-71
LGPL[0:5] Signal Negation (LAST) ............................................................... 14-71
Wait Mechanism (WAEN) ............................................................................... 14-71
RAM Array) ................................................................................................ 14-63
RAM Array) ................................................................................................ 14-63
Contents
Title
Number
Page
xxv