MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 334

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DDR Memory Controller
Table 9-7
9-12
Offset 0x080, 0x084, 0x088, 0x08C
Reset
Reset
13–15
16–17
9–11
Bits
1–7
12
0
8
W
W
R
R
CS_ n _ EN
BA_BITS_CS_ n
BA_BITS_CS_ n
ODT_WR_CFG
describes the CSn_CONFIG register fields.
ODT_RD_CFG
16
0
CS_ n _EN
AP_ n _EN
Name
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
—
17
1
Figure 9-3. Chip Select Configuration Register (CS n _CONFIG)
18
Chip select n enable
0 Chip select n is not active
1 Chip select n is active and assumes the state set in CS n _BNDS.
Reserved
Chip select n auto-precharge enable
0 Chip select n will only be auto-precharged if global auto-precharge mode is enabled
1 Chip select n will always issue an auto-precharge for read and write transactions.
3 cycles for ODT_RD_CFG to be enabled. ODT should only be used with DDR2 memories.
000 Never assert ODT for reads
001 Assert ODT only during reads to CS n
010 Assert ODT only during reads to other chip selects
011 Assert ODT only during reads to other DIMM modules. It is assumed that CS0 and CS1 are
100 Assert ODT for all reads
101–111 Reserved
Reserved
ODT for writes configuration. Note that write latency plus additive latency must be at least
3 cycles for ODT _WR_CFG to be enabled. ODT should only be used with DDR2 memories.
000 Never assert ODT for writes
001 Assert ODT only during writes to CS n
010 Assert ODT only during writes to other chip selects
011 Assert ODT only during writes to other DIMM modules. It is assumed that CS0 and CS1
100 Assert ODT for all writes
101–111 Reserved
Number of bank bits for SDRAM on chip select n . These bits correspond to the sub-bank bits
driven on MBA n in
00 2 logical bank bits
01 3 logical bank bits
10–11 Reserved
ODT for reads configuration. Note that CAS latency plus additive latency must be at least
(DDR_SDRAM_INTERVAL[BSTOPRE] = 0).
—
on the same DIMM module, whereas CS2 and CS3 are on a separate DIMM module.
are on the same DIMM module, whereas CS2 and CS3 are on a separate DIMM module.
Table 9-7. CS n _CONFIG Field Descriptions
—
20
ROW_BITS_CS_ n
21
Table 9-42Table
All zeros
All zeros
23
7
9-41and
AP_ n _EN
24
8
Description
Table
ODT_RD_CFG
9-42.
9
—
11
—
12
28
Freescale Semiconductor
Access: Read/Write
COL_BITS_CS_ n
ODT_WR_CFG
13
29
15
31