MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 26

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Paragraph
Number
14.5.1.4
14.5.2
14.5.2.1
14.5.2.2
14.5.2.3
14.5.2.4
14.5.3
14.5.4
14.5.4.1
14.5.4.2
14.5.4.3
14.5.4.3.1
14.5.4.3.2
14.5.4.3.3
14.5.4.3.4
14.5.4.3.5
14.5.4.3.6
14.5.4.3.7
14.5.4.3.8
14.5.4.4
14.5.5
14.5.6
14.5.6.1
14.5.6.1.1
14.5.6.1.2
14.5.6.1.3
14.5.6.1.4
14.5.6.2
14.5.6.2.1
14.5.6.2.2
14.5.6.2.3
15.1
15.2
15.3
15.4
15.4.1
15.5
xxvi
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Overview........................................................................................................................ 15-1
Features .......................................................................................................................... 15-2
Modes of Operation ....................................................................................................... 15-4
External Signals Description ......................................................................................... 15-6
Memory Map/Register Definition ............................................................................... 15-12
Bus Turnaround ....................................................................................................... 14-82
Interface to Different Port-Size Devices.................................................................. 14-83
Interfacing to SDRAM............................................................................................. 14-85
Interfacing to ZBT SRAM....................................................................................... 14-96
Interfacing to DSP Host Ports.................................................................................. 14-98
Detailed Signal Descriptions ..................................................................................... 15-8
GPCM Timings.................................................................................................... 14-81
Address Phase After Previous Read .................................................................... 14-82
Read Data Phase After Address Phase ................................................................ 14-82
Read-Modify-Write Cycle for Parity Protected Memory Banks ......................... 14-83
UPM Cycles with Additional Address Phases..................................................... 14-83
Basic SDRAM Capabilities of the Local Bus...................................................... 14-85
Maximum Amount of SDRAM Supported.......................................................... 14-86
SDRAM Machine Limitations............................................................................. 14-87
Parity Support for SDRAM ................................................................................. 14-95
Interfacing to MSC8101 HDI16 .......................................................................... 14-98
Interfacing to MSC8102 DSI............................................................................. 14-102
Analysis of Maximum Row Number Due to Bank Select Multiplexing......... 14-87
Bank Select Signals ......................................................................................... 14-87
128-Mbyte SDRAM ........................................................................................ 14-88
256-Mbyte SDRAM ........................................................................................ 14-90
512-Mbyte SDRAM ........................................................................................ 14-90
Power-Down Mode.......................................................................................... 14-91
Self-Refresh ..................................................................................................... 14-92
SDRAM Timing .............................................................................................. 14-93
HDI16 Peripherals ........................................................................................... 14-98
Physical Interconnections ................................................................................ 14-99
Supporting Burst Transfers............................................................................ 14-101
Host 60x Bus: HDI16 Peripheral Interface Hardware Timings..................... 14-101
DSI in Asynchronous SRAM-Like Mode ..................................................... 14-102
DSI in Synchronous Mode ............................................................................ 14-105
Broadcast Accesses.........................................................................................14-111
Enhanced Three-Speed Ethernet Controllers
Contents
Chapter 15
Title
Freescale Semiconductor
Number
Page