MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 726

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
This section describes synchronous single write and read, and synchronous burst write and read operations.
The local bus supports the DSI single strobe as well as the DSI double strobes of operation. The dual strobe
configuration is shown as an example.
Synchronous Single Write
Figure 14-87
The DSI samples HA, HDST, HCID, HD, HWBE, HRDE, and HBRST on the first HCLKIN rising edge
on which HCS is asserted. If HCID[0:3] match the CHIPID value, the DSI is accessed. At least one HWBE
signal is asserted, and HRDE and HBRST are negated. Assertion of HTA indicates that the DSI is ready
to complete the current access and the host must terminate this access. Because HTA is connected to the
LUPWAIT signal of the UPM, all local bus signals are frozen until HTA goes to 0 and then the UPM
continues in its pattern. Typically, HTA is asserted immediately. If the write buffer is full, HTA assertion
is delayed. HTA is asserted for one HCLKIN cycle, driven to logic 1 in the next cycle, and stops being
driven on the next rising edge of HCLKIN. The host can start its next access to the same MSC8102
immediately on the next HCLKIN rising edge without negating HCS between accesses. If the next access
is not to the same MSC8102, then, to prevent contention on HTA, the host must wait to access the next
device until the previous DSI stops driving HTA. The easiest way to achieve this is to insert idle cycles at
the end of the UPM pattern to guarantee that HTA is inactive.
14-108
HWBE[0:7]
Legend:
HDST[0:1]
Timing conventions:
HA[11:29]
HCID[0:3]
shows a synchronous single write access.
HD[0:63]
1
0
1
0
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
HCLKIN
HBRST
HRDE
HCS
HTA
Figure 14-87. Synchronous Single Write to MSC8102 DSI
Valid value that can be 1 or 0
Don’t care
Three-state output signal that is not driven by the DSI
Freescale Semiconductor