MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 30

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Paragraph
Number
15.5.3.10.1
15.5.3.10.2
15.5.4
15.5.4.1
15.5.4.1.1
15.5.4.1.2
15.5.4.1.3
15.5.4.2
15.5.4.2.1
15.5.4.2.2
15.5.4.3
15.5.4.3.1
15.5.4.3.2
15.5.4.3.3
15.5.4.3.4
15.5.4.3.5
15.5.4.3.6
15.5.4.3.7
15.5.4.3.8
15.5.4.3.9
15.5.4.3.10
15.6
15.6.1
15.6.1.1
15.6.1.2
15.6.1.3
15.6.1.4
15.6.1.5
15.6.1.6
15.6.1.7
15.6.2
15.6.2.1
15.6.2.2
15.6.2.3
15.6.2.4
15.6.2.5
15.6.3
15.6.3.1
15.6.3.1.1
15.6.3.1.2
xxx
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Functional Description............................................................................................... 15-126
Ten-Bit Interface (TBI) .......................................................................................... 15-114
Connecting to Physical Interfaces on Ethernet ...................................................... 15-126
Connecting to FIFO Interfaces .............................................................................. 15-137
Gigabit Ethernet Controller Channel Operation .................................................... 15-141
TBI Transmit Process ........................................................................................ 15-114
TBI Receive Process.......................................................................................... 15-115
TBI MII Set Register Descriptions .................................................................... 15-115
Media-Independent Interface (MII) ................................................................... 15-127
Reduced Media-Independent Interface (RMII) ................................................. 15-127
Gigabit Media-Independent Interface (GMII) ................................................... 15-128
Reduced Gigabit Media-Independent Interface (RGMII) ................................. 15-129
Ten-Bit Interface (TBI)...................................................................................... 15-131
Reduced Ten-Bit Interface (RTBI) .................................................................... 15-132
Ethernet Physical Interfaces Signal Summary................................................... 15-133
Flow Control...................................................................................................... 15-138
CRC Appending and Checking ......................................................................... 15-138
8-Bit GMII-Style Packet FIFO Mode................................................................ 15-139
8-Bit Encoded Packet FIFO Mode .................................................................... 15-140
FIFO Interface Signal Summary........................................................................ 15-140
Initialization Sequence....................................................................................... 15-141
Receive Queue Parameters 0–7 (RQPRM0–PQPRM7) ................................ 15-112
Receive Free Buffer Descriptor Pointer Registers 0–7
Packet Encapsulation..................................................................................... 15-114
8B10B Encoding............................................................................................ 15-114
Preamble Shortening...................................................................................... 15-114
Synchronization ............................................................................................. 15-115
Auto-Negotiation for 1000BASE-X.............................................................. 15-115
Control Register (CR).................................................................................... 15-116
Status Register (SR)....................................................................................... 15-117
AN Advertisement Register (ANA) .............................................................. 15-118
AN Link Partner Base Page Ability Register (ANLPBPA)........................... 15-120
AN Expansion Register (ANEX) .................................................................. 15-121
AN Next Page Transmit Register (ANNPT).................................................. 15-122
AN Link Partner Ability Next Page Register (ANLPANP) .......................... 15-123
Extended Status Register (EXST) ................................................................. 15-123
Jitter Diagnostics Register (JD) ..................................................................... 15-124
TBI Control Register (TBICON)................................................................... 15-125
Hardware Controlled Initialization................................................................ 15-141
User Initialization .......................................................................................... 15-141
(RFBPTR0–RFBPTR7) ............................................................................. 15-113
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