MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 330

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DDR Memory Controller
9-8
MODT[0:3]
MDIC[0:1]
MDM[0:8]
MCS[0:3]
Signal
MWE
Table 9-3. Memory Interface Signals—Detailed Signal Descriptions (continued)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
I/O Driver impedance calibration. Note that the MDIC signals require the use of 18.2-Ω precision 1%
O
O
O
O
Chip selects. Four chip selects supported by the memory controller.
Write enable. Asserted when a write transaction is issued to the SDRAM. This is also used for mode
registers set commands and precharge commands.
DDR SDRAM data output mask. Masks unwanted bytes of data transferred during a write. They are
needed to support sub-burst-size transactions (such as single-byte writes) on SDRAM where all I/O
occurs in multi-byte bursts. MDM0 corresponds to the most significant byte (MSB) and MDM7
corresponds to the LSB, while MDM8 corresponds to the ECC byte.
encodings.
On-Die termination. Memory controller outputs for the ODT to the DRAM. MODT[0:3] represents the
on-die termination for the associated data, data masks, ECC, and data strobes.
resistors; MDIC0 must be pulled to GND, while MDIC1 must be pulled to GV
“DDR Control Driver Register
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—Asserted to signal any new transaction to the SDRAM. The transaction
Timing Assertion/Negation—Similar timing as MRAS and MCAS. Used for write commands.
Timing Assertion/Negation—Same timing as MDQx as outputs.
Timing Assertion/Negation—Driven in accordance with JEDEC DRAM specifications for on-die
Timing These will be driven for four DRAM cycles at a time while the DDR controller is executing the
State
State
State
State
State
Asserted—Selects a physical SDRAM bank to perform a memory operation as described in
Negated—Indicates no SDRAM action during the current cycle.
High impedance—Always driven unless the memory controller is disabled.
Asserted—Indicates a memory write operation. See
Negated—Indicates a memory read operation.
High impedance—MWE is always driven unless the memory controller is disabled.
Asserted—Prevents writing to DDR SDRAM. Asserted when data is written to DRAM if the
Negated—Allows the corresponding byte to be read from or written to the SDRAM.
High impedance—Always driven unless the memory controller is disabled.
Asserted/Negated—Represents the ODT driven by the DDR memory controller.
High impedance—Always driven.
These pins are used for automatic calibration of the DDR IOs.
Section 9.4.1.1, “Chip Select Memory Bounds (CSn_BNDS),”
“Chip Select Configuration (CSn_CONFIG).”
MCS[0:3] signals to begin a memory cycle.
must adhere to the timing constraints set in TIMING_CFG_0–TIMING_CFG_3.
states required on MWE for various other SDRAM commands.
corresponding byte(s) should be masked for the write. Note that the MDM n signals are
active-high for the DDR controller. MDM n is part of the DDR command encoding.
termination timings. It is configured through the CS n _CONFIG[ODT_RD_CFG] and
CS n _CONFIG[ODT_WR_CFG] fields.
automatic driver compensation.
(DDRCDR),” for more information on these signals.
Description
The DDR controller asserts one of the
Table 9-46
Table 9-38
for more information on the
DD
Freescale Semiconductor
. See
and
shows byte lane
Section 9.4.1.2,
Section 19.4.1.21,