MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1049

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Chapter 18
PCI Express Interface Controller
The PCI Express interface complies with the PCI Express™ Base Specification, Revision 1.0a (available
from http://www.pcisig.org). It is beyond the scope of this manual to document the intricacies of the PCI
Express protocol. This chapter describes the PCI Express controller of this device and provides a basic
description of the PCI Express protocol. The specific emphasis is directed at how the device implements
the PCI Express specification. Designers of systems incorporating PCI Express devices should refer to the
specification for a thorough description of PCI Express.
18.1
The PCI Express controller provides the mechanism to communicate with PCI Express devices.
Figure 18-1
18.1.1
The PCI Express controller connects the internal platform to a 2.5-GHz serial interface. The MPC8533E
offers three instantiations of this controller yielding up to two x4 links supported on SerDes 1 and a single
x1 link on SerDes 2.The remainder of this chapter refers to a single PCI Express controller offering up to
a x8 link interface. Notes are included to indicate variations for multiple instantiations.
As both an initiator and a target device, the PCI Express interface is capable of high-bandwidth data
transfer and is designed to support next generation I/O devices. Upon coming out of reset, the PCI Express
interface performs link width negotiation and exchanges flow control credits with its link partner. Once
link autonegotiation is successful, the controller is in operation.
Internally, the design contains queues to keep track of inbound and outbound transactions. There is control
logic that handles buffer management, bus protocol, transaction spawning and tag generation. In addition,
there are memory blocks used to store inbound and outbound data.
The PCI Express controller can be configured to operate as either a PCI Express root complex (RC) or an
endpoint (EP) device. An RC device connects the host CPU/memory subsystem to I/O devices while an
Freescale Semiconductor
Introduction
Overview
is a high-level block diagram of the PCI Express controller.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Much of the available PCI Express literature refers to a 16-bit quantity as a
WORD and a 32-bit quantity as a DWORD. Note that this is inconsistent
with the terminology in the rest of this manual where the terms ‘word’ and
‘double word’ refer to a 32-bit and 64-bit quantity, respectively. Where
necessary to avoid confusion, the precise number of bits or bytes is
specified.
NOTE
18-1