EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 14

• Manufacturer Part Number: EZ80F91AZA50EG
• Description: IC ACCLAIM MCU 256KB 144LQFP
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91AZA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4563

PS027001-0707
Table 2. Pin Identification on the eZ80F91 Device
LQFP
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Characteristics
BGA
Pin No Symbol
A1
B1
B2
C3
D4
C1
C2
E5
D2
D1
D3
F6
E1
E2
E3
E4
Table 2
ball BGA package.
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
V
V
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
V
V
ADDR11
DD
SS
DD
SS
describes the pins and functions of the eZ80F91 144-pin LQFP package and 144-
Function
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Power Supply
Ground
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Power Supply
Ground
Address Bus
Signal Direction Description
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Configured as an output in normal
operation. The address bus selects
a location in memory or I/O space to
be read or written. Configured as an
input during bus acknowledge
cycles. Drives the Chip Select/Wait
State Generator block to generate
Chip Selects.
Power Supply.
Ground.
Configured as an output in normal
operation. The address bus selects
a location in memory or I/O space to
be read or written. Configured as an
input during bus acknowledge
cycles. Drives the Chip Select/Wait
State Generator block to generate
Chip Selects.
Power Supply.
Ground.
Configured as an output in normal
operation. The address bus selects
a location in memory or I/O space to
be read or written. Configured as an
input during bus acknowledge
cycles. Drives the Chip Select/Wait
State Generator block to generate
Chip Selects.
Product Specification
Architectural Overview
eZ80F91 ASSP
6